Console Output

+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p pulpino -b digilent_arty_a7_100t
Final configuration file generated at /var/jenkins_home/workspace/pulpino/pulpino/build_digilent_arty_a7_100t.tcl
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'axi_bus.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/axi2apb_wrap.sv:11]
ERROR: [Synth 8-9263] cannot open include file 'axi_bus.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/axi_mem_if_SP_wrap.sv:11]
ERROR: [Synth 8-9263] cannot open include file 'axi_bus.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/axi_node_intf_wrap.sv:12]
ERROR: [Synth 8-9263] cannot open include file 'config.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/boot_rom_wrap.sv:12]
ERROR: [Synth 8-9263] cannot open include file 'axi_bus.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/core2axi_wrap.sv:12]
ERROR: [Synth 8-9263] cannot open include file 'axi_bus.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/core_region.sv:12]
ERROR: [Synth 8-9263] cannot open include file 'config.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/core_region.sv:13]
ERROR: [Synth 8-9263] cannot open include file 'config.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/dp_ram_wrap.sv:12]
ERROR: [Synth 8-9263] cannot open include file 'config.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/instr_ram_wrap.sv:12]
ERROR: [Synth 8-9263] cannot open include file 'apb_bus.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/periph_bus_wrap.sv:11]
ERROR: [Synth 8-9263] cannot open include file 'axi_bus.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/peripherals.sv:11]
ERROR: [Synth 8-9263] cannot open include file 'apb_bus.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/peripherals.sv:12]
ERROR: [Synth 8-9263] cannot open include file 'debug_bus.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/peripherals.sv:13]
ERROR: [Synth 8-9263] cannot open include file 'config.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/peripherals.sv:14]
ERROR: [Synth 8-9263] cannot open include file 'axi_bus.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/pulpino_top.sv:11]
ERROR: [Synth 8-9263] cannot open include file 'debug_bus.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/pulpino_top.sv:12]
ERROR: [Synth 8-9263] cannot open include file 'config.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/sp_ram_wrap.sv:11]
ERROR: [Synth 8-9263] cannot open include file 'axi_bus.sv' [/var/jenkins_home/workspace/pulpino/pulpino/rtl/axi2apb_wrap.sv:11]
ERROR: [Synth 8-439] module 'processorci_top' not found
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 307, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.