Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s -I rtl/includes/ rtl/apb_mock_uart.sv rtl/axi2apb_wrap.sv rtl/axi_mem_if_SP_wrap.sv rtl/axi_node_intf_wrap.sv rtl/axi_slice_wrap.sv rtl/axi_spi_slave_wrap.sv rtl/boot_code.sv rtl/boot_rom_wrap.sv rtl/clk_rst_gen.sv rtl/core2axi_wrap.sv rtl/core_region.sv rtl/dp_ram_wrap.sv rtl/instr_ram_wrap.sv rtl/periph_bus_wrap.sv rtl/peripherals.sv rtl/pulpino_top.sv rtl/ram_mux.sv rtl/random_stalls.sv rtl/sp_ram_wrap.sv rtl/components/cluster_clock_gating.sv rtl/components/cluster_clock_inverter.sv rtl/components/cluster_clock_mux2.sv rtl/components/dp_ram.sv rtl/components/generic_fifo.sv rtl/components/pulp_clock_gating.sv rtl/components/pulp_clock_inverter.sv rtl/components/pulp_clock_mux2.sv rtl/components/rstgen.sv rtl/components/sp_ram.sv rtl/includes/apb_bus.sv rtl/includes/apu_defines.sv rtl/includes/axi_bus.sv rtl/includes/config.sv rtl/includes/debug_bus.sv
rtl/axi2apb_wrap.sv:12: Include file axi_bus.sv not found
rtl/apb_mock_uart.sv:51: syntax error
rtl/apb_mock_uart.sv:50: error: Invalid module instantiation
rtl/apb_mock_uart.sv:56: syntax error
rtl/apb_mock_uart.sv:56: error: Invalid module instantiation
rtl/apb_mock_uart.sv:58: syntax error
rtl/apb_mock_uart.sv:58: error: Invalid module instantiation
rtl/apb_mock_uart.sv:64: error: Invalid module item.
rtl/apb_mock_uart.sv:68: syntax error
rtl/apb_mock_uart.sv:68: error: Invalid module instantiation
rtl/apb_mock_uart.sv:77: error: Invalid module item.
rtl/apb_mock_uart.sv:78: syntax error
rtl/apb_mock_uart.sv:81: error: Invalid module item.
rtl/apb_mock_uart.sv:89: syntax error
rtl/apb_mock_uart.sv:94: error: Invalid module item.