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Start of Pipeline - (40 min in block)
node - (40 min in block)
node block - (19 sec in block)
stage - (3.6 sec in block)Git Clone
stage block (Git Clone) - (3.1 sec in block)
sh - (1.5 sec in self)rm -rf pulpino
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/pulp-platform/pulpino pulpino
stage - (2 sec in block)Simulation
stage block (Simulation) - (1.4 sec in block)
dir - (1 sec in block)pulpino
dir block - (0.68 sec in block)
sh - (0.47 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s -I rtl/includes/ rtl/apb_mock_uart.sv rtl/axi2apb_wrap.sv rtl/axi_mem_if_SP_wrap.sv rtl/axi_node_intf_wrap.sv rtl/axi_slice_wrap.sv rtl/axi_spi_slave_wrap.sv rtl/boot_code.sv rtl/boot_rom_wrap.sv rtl/clk_rst_gen.sv rtl/core2axi_wrap.sv rtl/core_region.sv rtl/dp_ram_wrap.sv rtl/instr_ram_wrap.sv rtl/periph_bus_wrap.sv rtl/peripherals.sv rtl/pulpino_top.sv rtl/ram_mux.sv rtl/random_stalls.sv rtl/sp_ram_wrap.sv rtl/components/cluster_clock_gating.sv rtl/components/cluster_clock_inverter.sv rtl/components/cluster_clock_mux2.sv rtl/components/dp_ram.sv rtl/components/generic_fifo.sv rtl/components/pulp_clock_gating.sv rtl/components/pulp_clock_inverter.sv rtl/components/pulp_clock_mux2.sv rtl/components/rstgen.sv rtl/components/sp_ram.sv rtl/includes/apb_bus.sv rtl/includes/apu_defines.sv rtl/includes/axi_bus.sv rtl/includes/config.sv rtl/includes/debug_bus.sv
stage - (1 sec in block)Utilities
stage block (Utilities) - (0.37 sec in block)
getContext - (0.17 sec in self)
stage - (10 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (8.7 sec in block)
getContext - (0.27 sec in self)
parallel - (8.1 sec in block)
parallel block (Branch: colorlight_i9) - (59 ms in block)
stage - (6.6 sec in block)colorlight_i9
stage block (colorlight_i9) - (6.3 sec in block)
getContext - (0.66 sec in self)
stage - (1.7 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.6 sec in block)
getContext - (0.17 sec in self)
stage - (1.7 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.66 sec in block)
getContext - (0.17 sec in self)
stage - (1.2 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.61 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (7.4 sec in block)
stage - (6.6 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (6.1 sec in block)
getContext - (0.63 sec in self)
stage - (1.7 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.73 sec in block)
getContext - (0.16 sec in self)
stage - (1.7 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.72 sec in block)
getContext - (0.15 sec in self)
stage - (1.2 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.71 sec in block)
getContext - (0.16 sec in self)
stage - (1.3 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.73 sec in block)
junit - (0.26 sec in self)**/test-reports/*.xml