Skip to content
[Jenkins]Jenkins
log in
StepArgumentsStatus
Start of Pipeline - (3 hr 24 min in block)
node - (3 hr 24 min in block)
node block - (11 min in block)
stage - (2.9 sec in block)Git Clone
stage block (Git Clone) - (2.4 sec in block)
sh - (0.79 sec in self)rm -rf nerv
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/YosysHQ/nerv nerv
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.95 sec in block)
dir - (0.56 sec in block)nerv
dir block - (0.32 sec in block)
echo - (0.1 sec in self)simulation not supported for System Verilog files
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.89 sec in block)nerv
dir block - (0.64 sec in block)
sh - (0.42 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (10 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (10 min in block)
parallel - (10 min in block)
parallel block (Branch: colorlight_i9) - (51 ms in block)
stage - (15 sec in block)colorlight_i9
stage block (colorlight_i9) - (14 sec in block)
lock - (13 sec in block)colorlight_i9
lock block - (13 sec in block)
stage - (10 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (10 sec in block)
dir - (9.4 sec in block)nerv
dir block - (9.1 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (8.5 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p nerv -b colorlight_i9
stage - (1 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.42 sec in block)
getContext - (0.19 sec in self)
stage - (0.69 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.35 sec in block)
getContext - (0.15 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (10 min in block)
stage - (10 min in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (10 min in block)
lock - (10 min in block)digilent_arty_a7_100t
lock block - (10 min in block)
stage - (10 min in block)Synthesis and PnR
stage block (Synthesis and PnR) - (10 min in block)
dir - (10 min in block)nerv
dir block - (10 min in block)
echo - (0.17 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (10 min in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p nerv -b digilent_arty_a7_100t
stage - (5.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.6 sec in block)
dir - (4.2 sec in block)nerv
dir block - (4 sec in block)
echo - (0.16 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p nerv -b digilent_arty_a7_100t -l
stage - (7.3 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (7 sec in block)
echo - (0.22 sec in self)Testing FPGA digilent_arty_a7_100t.
dir - (6.5 sec in block)nerv
dir block - (6.2 sec in block)
sh - (0.46 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (5.6 sec in self)python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459
stage - (0.85 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.61 sec in block)
junit - (0.36 sec in self)**/*.xml