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+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p muntjac -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/muntjac/muntjac/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'tl_util.svh' [/var/jenkins_home/workspace/muntjac/muntjac/ip/axi/rtl/axi_tl_adapter.sv:1]
ERROR: [Synth 8-9263] cannot open include file 'tl_util.svh' [/var/jenkins_home/workspace/muntjac/muntjac/ip/axi/rtl/tl_axi_adapter.sv:1]
ERROR: [Synth 8-9263] cannot open include file 'tl_util.svh' [/var/jenkins_home/workspace/muntjac/muntjac/ip/axi/rtl/tl_axi_lite_adapter.sv:1]
ERROR: [Synth 8-9263] cannot open include file 'tl_util.svh' [/var/jenkins_home/workspace/muntjac/muntjac/ip/core/rtl/muntjac_core.sv:1]
ERROR: [Synth 8-9263] cannot open include file 'tl_util.svh' [/var/jenkins_home/workspace/muntjac/muntjac/ip/core/rtl/muntjac_dcache.sv:1]
ERROR: [Synth 8-9263] cannot open include file 'prim_assert.sv' [/var/jenkins_home/workspace/muntjac/muntjac/ip/core/rtl/muntjac_dcache.sv:2]
ERROR: [Synth 8-9263] cannot open include file 'tl_util.svh' [/var/jenkins_home/workspace/muntjac/muntjac/ip/core/rtl/muntjac_icache.sv:1]
ERROR: [Synth 8-9263] cannot open include file 'prim_assert.sv' [/var/jenkins_home/workspace/muntjac/muntjac/ip/core/rtl/muntjac_icache.sv:2]
ERROR: [Synth 8-9263] cannot open include file 'tl_util.svh' [/var/jenkins_home/workspace/muntjac/muntjac/ip/core/rtl/muntjac_icache_coherent.sv:1]
ERROR: [Synth 8-9263] cannot open include file 'prim_assert.sv' [/var/jenkins_home/workspace/muntjac/muntjac/ip/core/rtl/muntjac_icache_coherent.sv:2]
ERROR: [Synth 8-9263] cannot open include file 'prim_assert.sv' [/var/jenkins_home/workspace/muntjac/muntjac/ip/core/rtl/muntjac_llc.sv:1]
ERROR: [Synth 8-9263] cannot open include file 'tl_util.svh' [/var/jenkins_home/workspace/muntjac/muntjac/ip/core/rtl/muntjac_llc.sv:2]
ERROR: [Synth 8-9263] cannot open include file 'prim_assert.sv' [/var/jenkins_home/workspace/muntjac/muntjac/vendor/lowrisc_ip/prim_generic/rtl/prim_generic_flop.sv:5]
ERROR: [Synth 8-9263] cannot open include file 'prim_assert.sv' [/var/jenkins_home/workspace/muntjac/muntjac/vendor/lowrisc_ip/prim_generic/rtl/prim_generic_ram_1p.sv:7]
ERROR: [Synth 8-9263] cannot open include file 'prim_util_memload.svh' [/var/jenkins_home/workspace/muntjac/muntjac/vendor/lowrisc_ip/prim_generic/rtl/prim_generic_ram_1p.sv:60]
ERROR: [Synth 8-9263] cannot open include file 'prim_assert.sv' [/var/jenkins_home/workspace/muntjac/muntjac/vendor/lowrisc_ip/prim_generic/rtl/prim_generic_ram_2p.sv:8]
ERROR: [Synth 8-9263] cannot open include file 'prim_util_memload.svh' [/var/jenkins_home/workspace/muntjac/muntjac/vendor/lowrisc_ip/prim_generic/rtl/prim_generic_ram_2p.sv:89]
ERROR: [Synth 8-9263] cannot open include file 'prim_assert.sv' [/var/jenkins_home/workspace/muntjac/muntjac/vendor/lowrisc_ip/prim_generic/rtl/prim_generic_ram_simple_2p.sv:8]
ERROR: [Synth 8-9263] cannot open include file 'prim_util_memload.svh' [/var/jenkins_home/workspace/muntjac/muntjac/vendor/lowrisc_ip/prim_generic/rtl/prim_generic_ram_simple_2p.sv:65]
ERROR: [Synth 8-9263] cannot open include file 'tl_util.svh' [/var/jenkins_home/workspace/muntjac/muntjac/ip/axi/rtl/axi_tl_adapter.sv:1]
ERROR: [Synth 8-10157] use of undefined macro 'TL_DECLARE_HOST_PORT' [/var/jenkins_home/workspace/muntjac/muntjac/ip/axi/rtl/axi_tl_adapter.sv:17]
ERROR: [Synth 8-2716] syntax error near '(' [/var/jenkins_home/workspace/muntjac/muntjac/ip/axi/rtl/axi_tl_adapter.sv:17]
ERROR: [Synth 8-439] module 'Controller' not found [/eda/processor_ci/rtl/muntjac.sv:69]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/muntjac.sv:5]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 296, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.