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Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/mriscv [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf mriscv [Pipeline] sh + git clone --recursive --depth=1 https://github.com/onchipuis/mriscv mriscv Cloning into 'mriscv'... Submodule 'mriscvcore' (https://github.com/onchipuis/mriscvcore.git) registered for path 'mriscvcore' Cloning into '/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore'... Submodule path 'mriscvcore': checked out '1e94fa95bcdddb889be205ed661b9addff1221a4' [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/mriscv/mriscv [Pipeline] { [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s mriscvcore mriscvcore/mriscvcore.v mriscvcore/ALU/ALU.v mriscvcore/DECO_INSTR/DECO_INSTR.v mriscvcore/FSM/FSM.v mriscvcore/IRQ/IRQ.v mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v mriscvcore/MULT/MULT.v mriscvcore/REG_FILE/REG_FILE.v mriscvcore/UTILITIES/UTILITY.v mriscvcore/DECO_INSTR/DECO_INSTR.v:112: warning: Extra digits given for sized binary constant. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/mriscv/mriscv [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/mriscv/mriscv -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels WARNING: Error reading file /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR_tb.v with encoding utf-8: 'utf-8' codec can't decode byte 0xd3 in position 602: invalid continuation byte WARNING: Error reading file /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v with encoding utf-8: 'utf-8' codec can't decode byte 0xf3 in position 3316: invalid continuation byte Trying to read file: /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v Cache-related signals in axi4_interconnect.v Cache-related signals in priencr.v Cache-related signals in axi4_interconnect.v Results saved to /jenkins/processor_ci_utils/labels/mriscv.json [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] Resource [colorlight_i9] did not exist. Created. Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] Resource [digilent_arty_a7_100t] did not exist. Created. Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/mriscv/mriscv [Pipeline] { [Pipeline] dir Running in /var/jenkins_home/workspace/mriscv/mriscv [Pipeline] { [Pipeline] echo Starting synthesis for FPGA colorlight_i9. [Pipeline] sh [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p mriscv -b colorlight_i9 Final configuration file generated at /var/jenkins_home/workspace/mriscv/mriscv/build_colorlight_i9.tcl Error executing Makefile. ERROR: TCL interpreter returned an error: Yosys command produced an error make: *** [/eda/processor_ci/makefiles/colorlight_i9.mk:12: colorlight_i9.json] Error 1 Traceback (most recent call last): File "/eda/processor_ci/main.py", line 135, in <module> main( File "/eda/processor_ci/main.py", line 82, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor_ci/core/fpga.py", line 307, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p mriscv -b digilent_arty_a7_100t [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) Stage "Flash colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test colorlight_i9) Stage "Test colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch colorlight_i9 Final configuration file generated at /var/jenkins_home/workspace/mriscv/mriscv/build_digilent_arty_a7_100t.tcl Error executing Makefile. ERROR: [Common 17-69] Command failed: File '/eda/processor-ci-controller/modules/uart.v' does not exist make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1 Traceback (most recent call last): File "/eda/processor_ci/main.py", line 135, in <module> main( File "/eda/processor_ci/main.py", line 82, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor_ci/core/fpga.py", line 307, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch digilent_arty_a7_100t [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 9ce53990-884d-4c72-8dc2-86b46d5e529d hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 1 Finished: FAILURE