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Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130488.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130505.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130567.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130573.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130591.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130703.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130529.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130547.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130599.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130694.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130593.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$130421$lut$aiger130420$13423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Removed 0 unused cells and 12819 unused wires.
20.45. Executing AUTONAME pass.
Renamed 316160 objects in module processorci_top (177 iterations).
<suppressed ~19887 debug messages>
20.46. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `processorci_top'. Setting top module to processorci_top.
20.46.1. Analyzing design hierarchy..
Top module: \processorci_top
20.46.2. Analyzing design hierarchy..
Top module: \processorci_top
Removed 0 unused modules.
20.47. Printing statistics.
=== processorci_top ===
Number of wires: 9565
Number of wire bits: 25093
Number of public wires: 9565
Number of public wire bits: 25093
Number of ports: 10
Number of port bits: 10
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 11816
$scopeinfo 38
CCU2C 246
L6MUX21 844
LUT4 6845
PFUMX 1862
TRELLIS_DPR16X4 1060
TRELLIS_FF 921
20.48. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Found and reported 0 problems.
20.49. Executing JSON backend.
Warnings: 109 unique messages, 109 total
End of script. Logfile hash: 5750303554, CPU: user 38.92s system 0.26s, MEM: 293.29 MB peak
Time spent: 26% 1x abc9_exe (10 sec), 16% 11x techmap (6 sec), ...
/eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \
--lpf /eda/processor_ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \
--speed 6 --lpf-allow-unconstrained --ignore-loops
/eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config --bit colorlight_i9.bit
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] dir
Running in /var/jenkins_home/workspace/mriscv/mriscv
[Pipeline] {
[Pipeline] echo
Flashing FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p mriscv -b colorlight_i9 -l
Final configuration file generated at /var/jenkins_home/workspace/mriscv/mriscv/build_colorlight_i9.tcl
Makefile executed successfully.
Makefile output:
/eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 (null)
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
Loading: [==== ] 7.96%
Loading: [======== ] 15.92%
Loading: [============ ] 23.29%
Loading: [================ ] 30.96%
Loading: [==================== ] 38.92%
Loading: [======================== ] 46.88%
Loading: [============================ ] 54.25%
Loading: [=============================== ] 61.92%
Loading: [=================================== ] 69.88%
Loading: [======================================= ] 77.84%
Loading: [=========================================== ] 85.50%
Loading: [=============================================== ] 93.17%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test colorlight_i9)
[Pipeline] echo
Testing FPGA colorlight_i9.
[Pipeline] dir
Running in /var/jenkins_home/workspace/mriscv/mriscv
[Pipeline] {
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyACM0
Test for FPGA in /dev/ttyACM0
[Pipeline] sh
+ python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0
Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'}
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Final configuration file generated at /var/jenkins_home/workspace/mriscv/mriscv/build_digilent_arty_a7_100t.tcl
Makefile executed successfully.
Makefile output:
Building the Design...
/eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/mriscv/mriscv/build_digilent_arty_a7_100t.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096"
****** Vivado v2023.2 (64-bit)
**** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source /var/jenkins_home/workspace/mriscv/mriscv/build_digilent_arty_a7_100t.tcl
# read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v
read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1308.113 ; gain = 0.023 ; free physical = 1887 ; free virtual = 23861
# read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v
# read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v
# read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v
# read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v
# read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v
# read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v
# read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v
# read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v
# read_verilog /eda/processor_ci/rtl/mriscv.v
# read_verilog /eda/processor-ci-controller/modules/uart.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
# read_verilog /eda/processor-ci-controller/src/fifo.v
# read_verilog /eda/processor-ci-controller/src/reset.v
# read_verilog /eda/processor-ci-controller/src/clk_divider.v
# read_verilog /eda/processor-ci-controller/src/memory.v
# read_verilog /eda/processor-ci-controller/src/interpreter.v
# read_verilog /eda/processor-ci-controller/src/controller.v
# set ID [lindex $argv 0]
# set CLOCK_FREQ [lindex $argv 1]
# set MEMORY_SIZE [lindex $argv 2]
# set HIGH_CLK 1
# read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
# set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
# synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE \
# -verilog_define $HIGH_CLK
Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096 -verilog_define 1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 3562716
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2031.812 ; gain = 403.660 ; free physical = 726 ; free virtual = 22712
---------------------------------------------------------------------------------
INFO: [Synth 8-11241] undeclared symbol 'rdw_rsrn', assumed default net type 'wire' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:130]
INFO: [Synth 8-11241] undeclared symbol 'enable_pc', assumed default net type 'wire' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:204]
INFO: [Synth 8-11241] undeclared symbol 'done_exec', assumed default net type 'wire' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:223]
INFO: [Synth 8-11241] undeclared symbol 'enable_exec', assumed default net type 'wire' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:231]
INFO: [Synth 8-11241] undeclared symbol 'enable_exec_mem', assumed default net type 'wire' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:232]
CRITICAL WARNING: [Synth 8-9339] data object 'reset_o' is already declared [/eda/processor_ci/rtl/mriscv.v:166]
INFO: [Synth 8-6826] previous declaration of 'reset_o' is from here [/eda/processor_ci/rtl/mriscv.v:29]
CRITICAL WARNING: [Synth 8-11152] second declaration of 'reset_o' is ignored [/eda/processor_ci/rtl/mriscv.v:166]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16]
WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15]
WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16]
WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17]
WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84]
WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85]
INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/mriscv.v:1]
INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
Parameter ID bound to: 0 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 4096 - type: integer
INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1]
Parameter COUNTER_BITS bound to: 32 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1]
INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter ID bound to: 0 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213]
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1]
Parameter DEPTH bound to: 8 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1]
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 4096 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1]
WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268]
INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1]
INFO: [Synth 8-6157] synthesizing module 'mriscvcore' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:10]
INFO: [Synth 8-6157] synthesizing module 'MEMORY_INTERFACE' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:3]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:225]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:256]
INFO: [Synth 8-6155] done synthesizing module 'MEMORY_INTERFACE' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:3]
INFO: [Synth 8-6157] synthesizing module 'DECO_INSTR' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:3]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:28]
INFO: [Synth 8-6155] done synthesizing module 'DECO_INSTR' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:3]
INFO: [Synth 8-6157] synthesizing module 'REG_FILE' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:40]
INFO: [Synth 8-6157] synthesizing module 'true_dpram_sclk' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:17]
INFO: [Synth 8-6155] done synthesizing module 'true_dpram_sclk' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:17]
INFO: [Synth 8-6155] done synthesizing module 'REG_FILE' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:40]
INFO: [Synth 8-6157] synthesizing module 'ALU' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'ALU_add' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:387]
Parameter REG_ALU bound to: 1'b1
Parameter REG_OUT bound to: 1'b1
INFO: [Synth 8-6155] done synthesizing module 'ALU_add' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:387]
INFO: [Synth 8-6157] synthesizing module 'ALU_sub' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:419]
Parameter REG_ALU bound to: 1'b1
Parameter REG_OUT bound to: 1'b1
INFO: [Synth 8-6155] done synthesizing module 'ALU_sub' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:419]
INFO: [Synth 8-6157] synthesizing module 'ALU_and' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:450]
Parameter REG_ALU bound to: 1'b1
Parameter REG_OUT bound to: 1'b1
INFO: [Synth 8-6155] done synthesizing module 'ALU_and' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:450]
INFO: [Synth 8-6157] synthesizing module 'ALU_xor' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:481]
Parameter REG_ALU bound to: 1'b1
Parameter REG_OUT bound to: 1'b1
INFO: [Synth 8-6155] done synthesizing module 'ALU_xor' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:481]
INFO: [Synth 8-6157] synthesizing module 'ALU_or' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:512]
Parameter REG_ALU bound to: 1'b1
Parameter REG_OUT bound to: 1'b1
INFO: [Synth 8-6155] done synthesizing module 'ALU_or' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:512]
INFO: [Synth 8-6157] synthesizing module 'ALU_beq' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:543]
Parameter REG_ALU bound to: 1'b1
Parameter REG_OUT bound to: 1'b1
INFO: [Synth 8-6155] done synthesizing module 'ALU_beq' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:543]
INFO: [Synth 8-6157] synthesizing module 'ALU_blt' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:561]
Parameter REG_ALU bound to: 1'b1
Parameter REG_OUT bound to: 1'b1
INFO: [Synth 8-6155] done synthesizing module 'ALU_blt' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:561]
INFO: [Synth 8-6157] synthesizing module 'ALU_bltu' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:579]
Parameter REG_ALU bound to: 1'b1
Parameter REG_OUT bound to: 1'b1
INFO: [Synth 8-6155] done synthesizing module 'ALU_bltu' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:579]
INFO: [Synth 8-6157] synthesizing module 'ALU_sXXx' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:597]
Parameter REG_ALU bound to: 1'b1
Parameter REG_OUT bound to: 1'b1
INFO: [Synth 8-6155] done synthesizing module 'ALU_sXXx' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:597]
INFO: [Synth 8-6155] done synthesizing module 'ALU' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'IRQ' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:114]
INFO: [Synth 8-6157] synthesizing module 'Count' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:41]
INFO: [Synth 8-6157] synthesizing module 'divM' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:3]
INFO: [Synth 8-6155] done synthesizing module 'divM' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:3]
INFO: [Synth 8-6155] done synthesizing module 'Count' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:41]
INFO: [Synth 8-6155] done synthesizing module 'IRQ' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:114]
INFO: [Synth 8-6157] synthesizing module 'MULT' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:105]
INFO: [Synth 8-6157] synthesizing module 'FSM_Booth' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:3]
INFO: [Synth 8-6155] done synthesizing module 'FSM_Booth' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:3]
INFO: [Synth 8-6157] synthesizing module 'Alg_Booth' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:47]
INFO: [Synth 8-6155] done synthesizing module 'Alg_Booth' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:47]
INFO: [Synth 8-6157] synthesizing module 'FSM_Booth__parameterized0' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:3]
Parameter BITS_BOOTH bound to: 17 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FSM_Booth__parameterized0' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:3]
INFO: [Synth 8-6157] synthesizing module 'Alg_Booth__parameterized0' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:47]
Parameter SWORD bound to: 18 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Alg_Booth__parameterized0' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:47]
INFO: [Synth 8-6155] done synthesizing module 'MULT' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:105]
INFO: [Synth 8-6157] synthesizing module 'UTILITY' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:3]
INFO: [Synth 8-6155] done synthesizing module 'UTILITY' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:3]
INFO: [Synth 8-6157] synthesizing module 'FSM' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:3]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:77]
INFO: [Synth 8-6155] done synthesizing module 'FSM' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:3]
INFO: [Synth 8-6155] done synthesizing module 'mriscvcore' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:10]
WARNING: [Synth 8-7071] port 'outirr' of module 'mriscvcore' is unconnected for instance 'mriscvcore_inst' [/eda/processor_ci/rtl/mriscv.v:98]
WARNING: [Synth 8-7023] instance 'mriscvcore_inst' of module 'mriscvcore' has 22 connections declared, but only 21 given [/eda/processor_ci/rtl/mriscv.v:98]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1]
Parameter CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1]
WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/mriscv.v:170]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/mriscv.v:170]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/mriscv.v:170]
INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/mriscv.v:1]
WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25]
WARNING: [Synth 8-6014] Unused sequential element rdu_reg was removed. [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:324]
WARNING: [Synth 8-6014] Unused sequential element timer_count_reg was removed. [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:151]
WARNING: [Synth 8-6014] Unused sequential element aux_reg was removed. [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:79]
WARNING: [Synth 8-6014] Unused sequential element aux_reg was removed. [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:79]
WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/mriscv.v:21]
WARNING: [Synth 8-7129] Port busy_mem in module FSM is either unconnected or has no load
WARNING: [Synth 8-7129] Port is_exec in module FSM is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[31] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[30] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[29] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[28] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[27] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[26] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[25] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[24] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[23] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[22] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[21] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[20] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[19] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[18] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[17] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[16] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[15] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[14] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[13] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[12] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[11] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[10] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[9] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[8] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[7] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[6] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port oper2[5] in module ALU_sXXx is either unconnected or has no load
WARNING: [Synth 8-7129] Port clk in module ALU_bltu is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module ALU_bltu is either unconnected or has no load
WARNING: [Synth 8-7129] Port clk in module ALU_blt is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module ALU_blt is either unconnected or has no load
WARNING: [Synth 8-7129] Port clk in module ALU_beq is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module ALU_beq is either unconnected or has no load
WARNING: [Synth 8-7129] Port rst in module true_dpram_sclk is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port rw in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2130.750 ; gain = 502.598 ; free physical = 598 ; free virtual = 22586
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2148.562 ; gain = 520.410 ; free physical = 595 ; free virtual = 22582
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2148.562 ; gain = 520.410 ; free physical = 595 ; free virtual = 22582
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2148.562 ; gain = 0.000 ; free physical = 602 ; free virtual = 22589
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2298.312 ; gain = 0.000 ; free physical = 583 ; free virtual = 22570
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2298.348 ; gain = 0.000 ; free physical = 583 ; free virtual = 22570
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 472 ; free virtual = 22459
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 472 ; free virtual = 22459
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 472 ; free virtual = 22459
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'MEMORY_INTERFACE'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'FSM_Booth'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'FSM_Booth__parameterized0'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
READ | 001 | 0001
COPY_READ_BUFFER | 010 | 0100
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
COPY_WRITE_BUFFER | 001 | 0100
WRITE | 010 | 0001
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE | 0001 | 00
iSTATE0 | 0010 | 01
iSTATE1 | 0100 | 10
iSTATE2 | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
reposo | 000 | 0000
SR1 | 001 | 0010
SR2 | 010 | 0011
SW0 | 011 | 0101
SW1 | 100 | 0110
SW2 | 101 | 0111
SWB | 110 | 1000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'MEMORY_INTERFACE'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE1 | 00 | 00
iSTATE | 01 | 01
iSTATE0 | 10 | 10
iSTATE2 | 11 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'FSM_Booth'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE1 | 00 | 00
iSTATE | 01 | 01
iSTATE0 | 10 | 10
iSTATE2 | 11 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'FSM_Booth__parameterized0'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 457 ; free virtual = 22446
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 3
3 Input 64 Bit Adders := 1
4 Input 36 Bit Adders := 1
2 Input 33 Bit Adders := 1
2 Input 32 Bit Adders := 14
3 Input 32 Bit Adders := 1
2 Input 24 Bit Adders := 2
3 Input 18 Bit Adders := 1
2 Input 18 Bit Adders := 1
3 Input 17 Bit Adders := 2
2 Input 17 Bit Adders := 4
2 Input 10 Bit Adders := 2
2 Input 8 Bit Adders := 1
2 Input 6 Bit Adders := 4
2 Input 5 Bit Adders := 6
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 2
+---XORs :
2 Input 32 Bit XORs := 1
2 Input 1 Bit XORs := 1
+---Registers :
64 Bit Registers := 3
37 Bit Registers := 1
35 Bit Registers := 2
33 Bit Registers := 1
32 Bit Registers := 40
24 Bit Registers := 5
18 Bit Registers := 1
17 Bit Registers := 2
12 Bit Registers := 1
10 Bit Registers := 2
8 Bit Registers := 11
6 Bit Registers := 1
5 Bit Registers := 4
4 Bit Registers := 4
3 Bit Registers := 2
2 Bit Registers := 3
1 Bit Registers := 45
+---RAMs :
32K Bit (1024 X 32 bit) RAMs := 2
1024 Bit (32 X 32 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
4 Input 64 Bit Muxes := 1
2 Input 64 Bit Muxes := 2
48 Input 64 Bit Muxes := 2
3 Input 37 Bit Muxes := 1
6 Input 37 Bit Muxes := 1
4 Input 37 Bit Muxes := 1
2 Input 37 Bit Muxes := 1
2 Input 36 Bit Muxes := 1
3 Input 35 Bit Muxes := 2
6 Input 35 Bit Muxes := 2
4 Input 35 Bit Muxes := 2
2 Input 35 Bit Muxes := 2
2 Input 34 Bit Muxes := 2
2 Input 32 Bit Muxes := 45
5 Input 32 Bit Muxes := 2
3 Input 32 Bit Muxes := 3
4 Input 32 Bit Muxes := 4
11 Input 32 Bit Muxes := 1
12 Input 32 Bit Muxes := 1
26 Input 32 Bit Muxes := 1
10 Input 32 Bit Muxes := 1
48 Input 24 Bit Muxes := 1
2 Input 24 Bit Muxes := 4
2 Input 16 Bit Muxes := 2
2 Input 12 Bit Muxes := 9
2 Input 9 Bit Muxes := 1
48 Input 8 Bit Muxes := 2
2 Input 8 Bit Muxes := 4
24 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 2
2 Input 6 Bit Muxes := 4
3 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 27
11 Input 5 Bit Muxes := 1
3 Input 5 Bit Muxes := 1
9 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 4
3 Input 4 Bit Muxes := 2
5 Input 4 Bit Muxes := 1
11 Input 4 Bit Muxes := 2
26 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 4
2 Input 3 Bit Muxes := 7
26 Input 3 Bit Muxes := 1
4 Input 3 Bit Muxes := 3
6 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 25
48 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 8
3 Input 2 Bit Muxes := 2
9 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 96
48 Input 1 Bit Muxes := 22
3 Input 1 Bit Muxes := 7
4 Input 1 Bit Muxes := 5
5 Input 1 Bit Muxes := 12
7 Input 1 Bit Muxes := 8
26 Input 1 Bit Muxes := 3
6 Input 1 Bit Muxes := 1
8 Input 1 Bit Muxes := 9
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port busy_mem in module FSM is either unconnected or has no load
WARNING: [Synth 8-7129] Port is_exec in module FSM is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:23 ; elapsed = 00:01:25 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 406 ; free virtual = 22418
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1 | LUT |
|Interpreter | memory_mux_selector | 256x1 | LUT |
+------------+---------------------+---------------+----------------+
Block RAM: Preliminary Mapping Report (see note below)
+----------------+--------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+----------------+--------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|mriscvcore_inst | REG_FILE_inst/MEM_FILE/ram_reg | 32 x 32(READ_FIRST) | W | R | 32 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
+----------------+--------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
Distributed RAM: Preliminary Mapping Report (see note below)
+----------------+------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------+------------------------------------+-----------+----------------------+------------------+
|processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
|processorci_top | Controller/Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+----------------+------------------------------------+-----------+----------------------+------------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:35 ; elapsed = 00:01:37 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 401 ; free virtual = 22413
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:48 ; elapsed = 00:01:50 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 391 ; free virtual = 22404
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Block RAM: Final Mapping Report
+----------------+--------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+----------------+--------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|mriscvcore_inst | REG_FILE_inst/MEM_FILE/ram_reg | 32 x 32(READ_FIRST) | W | R | 32 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
+----------------+--------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Distributed RAM: Final Mapping Report
+----------------+------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------+------------------------------------+-----------+----------------------+------------------+
|processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
|processorci_top | Controller/Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+----------------+------------------------------------+-----------+----------------------+------------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-7052] The timing for the instance mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:55 ; elapsed = 00:01:57 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 390 ; free virtual = 22403
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:02:05 ; elapsed = 00:02:07 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 401 ; free virtual = 22413
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:02:05 ; elapsed = 00:02:07 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 401 ; free virtual = 22413
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:07 ; elapsed = 00:02:09 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 395 ; free virtual = 22408
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:02:07 ; elapsed = 00:02:10 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 392 ; free virtual = 22404
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 392 ; free virtual = 22405
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 389 ; free virtual = 22402
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 276|
|3 |LUT1 | 159|
|4 |LUT2 | 472|
|5 |LUT3 | 584|
|6 |LUT4 | 444|
|7 |LUT5 | 298|
|8 |LUT6 | 1096|
|9 |MUXF7 | 37|
|10 |RAM256X1S | 256|
|11 |RAM32M | 2|
|12 |RAM32X1D | 4|
|13 |RAMB36E1 | 1|
|14 |FDRE | 1548|
|15 |FDSE | 15|
|16 |IBUF | 2|
|17 |OBUF | 1|
|18 |OBUFT | 2|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 402 ; free virtual = 22415
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 35 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:02:02 ; elapsed = 00:02:04 . Memory (MB): peak = 2298.348 ; gain = 520.410 ; free physical = 386 ; free virtual = 22399
Synthesis Optimization Complete : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2298.348 ; gain = 670.195 ; free physical = 386 ; free virtual = 22399
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2298.348 ; gain = 0.000 ; free physical = 681 ; free virtual = 22694
INFO: [Netlist 29-17] Analyzing 576 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2362.344 ; gain = 0.000 ; free physical = 680 ; free virtual = 22692
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 262 instances were transformed.
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 806e8896
INFO: [Common 17-83] Releasing license: Synthesis
117 Infos, 125 Warnings, 4 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:02:27 ; elapsed = 00:02:24 . Memory (MB): peak = 2362.379 ; gain = 1054.266 ; free physical = 683 ; free virtual = 22696
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2059.460; main = 1766.595; forked = 434.761
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3248.602; main = 2362.348; forked = 982.301
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2426.375 ; gain = 63.996 ; free physical = 678 ; free virtual = 22691
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1ef27351b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2532.188 ; gain = 105.812 ; free physical = 625 ; free virtual = 22637
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 1ef27351b
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2781.094 ; gain = 0.000 ; free physical = 347 ; free virtual = 22360
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1ef27351b
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2781.094 ; gain = 0.000 ; free physical = 346 ; free virtual = 22359
Phase 1 Initialization | Checksum: 1ef27351b
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2781.094 ; gain = 0.000 ; free physical = 346 ; free virtual = 22359
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 1ef27351b
Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2781.094 ; gain = 0.000 ; free physical = 353 ; free virtual = 22366
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 1ef27351b
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2781.094 ; gain = 0.000 ; free physical = 353 ; free virtual = 22366
Phase 2 Timer Update And Timing Data Collection | Checksum: 1ef27351b
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2781.094 ; gain = 0.000 ; free physical = 353 ; free virtual = 22366
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 1 inverters resulting in an inversion of 7 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 17fc5446e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.88 . Memory (MB): peak = 2781.094 ; gain = 0.000 ; free physical = 353 ; free virtual = 22366
Retarget | Checksum: 17fc5446e
INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 6 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 141701c09
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2781.094 ; gain = 0.000 ; free physical = 353 ; free virtual = 22366
Constant propagation | Checksum: 141701c09
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 1249ea0bd
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2781.094 ; gain = 0.000 ; free physical = 353 ; free virtual = 22366
Sweep | Checksum: 1249ea0bd
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 1249ea0bd
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2813.109 ; gain = 32.016 ; free physical = 353 ; free virtual = 22366
BUFG optimization | Checksum: 1249ea0bd
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 1249ea0bd
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2813.109 ; gain = 32.016 ; free physical = 353 ; free virtual = 22366
Shift Register Optimization | Checksum: 1249ea0bd
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 1249ea0bd
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2813.109 ; gain = 32.016 ; free physical = 353 ; free virtual = 22366
Post Processing Netlist | Checksum: 1249ea0bd
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 129bae359
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2813.109 ; gain = 32.016 ; free physical = 353 ; free virtual = 22366
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2813.109 ; gain = 0.000 ; free physical = 353 ; free virtual = 22366
Phase 9.2 Verifying Netlist Connectivity | Checksum: 129bae359
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2813.109 ; gain = 32.016 ; free physical = 353 ; free virtual = 22366
Phase 9 Finalization | Checksum: 129bae359
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2813.109 ; gain = 32.016 ; free physical = 353 ; free virtual = 22366
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 4 | 6 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 129bae359
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2813.109 ; gain = 32.016 ; free physical = 353 ; free virtual = 22366
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2813.109 ; gain = 0.000 ; free physical = 353 ; free virtual = 22366
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2
Ending PowerOpt Patch Enables Task | Checksum: 129bae359
Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 341 ; free virtual = 22357
Ending Power Optimization Task | Checksum: 129bae359
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2989.164 ; gain = 176.055 ; free physical = 341 ; free virtual = 22357
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 129bae359
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 341 ; free virtual = 22357
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 341 ; free virtual = 22357
Ending Netlist Obfuscation Task | Checksum: 129bae359
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 341 ; free virtual = 22357
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 2989.164 ; gain = 626.785 ; free physical = 341 ; free virtual = 22357
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 336 ; free virtual = 22352
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: bb7ce5c3
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 336 ; free virtual = 22352
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 335 ; free virtual = 22351
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 120c36afa
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 341 ; free virtual = 22358
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1476cd24a
Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 337 ; free virtual = 22354
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1476cd24a
Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 335 ; free virtual = 22351
Phase 1 Placer Initialization | Checksum: 1476cd24a
Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 332 ; free virtual = 22348
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 13e6b8d7b
Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 334 ; free virtual = 22350
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1bb18ff8b
Time (s): cpu = 00:00:17 ; elapsed = 00:00:12 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 326 ; free virtual = 22343
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1bb18ff8b
Time (s): cpu = 00:00:17 ; elapsed = 00:00:12 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 338 ; free virtual = 22354
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 216b04441
Time (s): cpu = 00:01:06 ; elapsed = 00:00:42 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 322 ; free virtual = 22339
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 68 LUTNM shape to break, 150 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 34, two critical 34, total 68, new lutff created 3
INFO: [Physopt 32-1138] End 1 Pass. Optimized 131 nets or LUTs. Breaked 68 LUTs, combined 63 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 325 ; free virtual = 22342
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 68 | 63 | 131 | 0 | 1 | 00:00:01 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 68 | 63 | 131 | 0 | 9 | 00:00:01 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1bb42a2b5
Time (s): cpu = 00:01:10 ; elapsed = 00:00:45 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 325 ; free virtual = 22342
Phase 2.4 Global Placement Core | Checksum: 10eb1536c
Time (s): cpu = 00:01:47 ; elapsed = 00:01:05 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 322 ; free virtual = 22339
Phase 2 Global Placement | Checksum: 10eb1536c
Time (s): cpu = 00:01:47 ; elapsed = 00:01:05 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 322 ; free virtual = 22339
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: c91e243b
Time (s): cpu = 00:01:50 ; elapsed = 00:01:07 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 323 ; free virtual = 22340
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b7d79388
Time (s): cpu = 00:01:56 ; elapsed = 00:01:11 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 321 ; free virtual = 22338
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1b28e29ad
Time (s): cpu = 00:01:56 ; elapsed = 00:01:11 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 321 ; free virtual = 22338
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 2035a2d93
Time (s): cpu = 00:01:56 ; elapsed = 00:01:11 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 321 ; free virtual = 22338
Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 20e3b4ac8
Time (s): cpu = 00:02:10 ; elapsed = 00:01:22 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 309 ; free virtual = 22325
Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1dd74cf19
Time (s): cpu = 00:02:14 ; elapsed = 00:01:25 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 315 ; free virtual = 22332
Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 18dc2bbc0
Time (s): cpu = 00:02:15 ; elapsed = 00:01:26 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 316 ; free virtual = 22332
Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 1b334c1f5
Time (s): cpu = 00:02:15 ; elapsed = 00:01:26 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 316 ; free virtual = 22332
Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 1b79de7c6
Time (s): cpu = 00:02:35 ; elapsed = 00:01:42 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 317 ; free virtual = 22333
Phase 3 Detail Placement | Checksum: 1b79de7c6
Time (s): cpu = 00:02:35 ; elapsed = 00:01:43 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 317 ; free virtual = 22333
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: f06b9f1c
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.548 | TNS=-738.193 |
Phase 1 Physical Synthesis Initialization | Checksum: 108ca20ac
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 316 ; free virtual = 22333
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 108ca20ac
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 316 ; free virtual = 22333
Phase 4.1.1.1 BUFG Insertion | Checksum: f06b9f1c
Time (s): cpu = 00:02:45 ; elapsed = 00:01:49 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 316 ; free virtual = 22333
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=-1.912. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: e9dc77d7
Time (s): cpu = 00:05:28 ; elapsed = 00:04:26 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 734 ; free virtual = 22796
Time (s): cpu = 00:05:28 ; elapsed = 00:04:26 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 734 ; free virtual = 22795
Phase 4.1 Post Commit Optimization | Checksum: e9dc77d7
Time (s): cpu = 00:05:28 ; elapsed = 00:04:26 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 747 ; free virtual = 22809
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: e9dc77d7
Time (s): cpu = 00:05:28 ; elapsed = 00:04:27 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 745 ; free virtual = 22806
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 2x2|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: e9dc77d7
Time (s): cpu = 00:05:29 ; elapsed = 00:04:27 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 742 ; free virtual = 22803
Phase 4.3 Placer Reporting | Checksum: e9dc77d7
Time (s): cpu = 00:05:29 ; elapsed = 00:04:27 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 748 ; free virtual = 22809
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 748 ; free virtual = 22809
Time (s): cpu = 00:05:29 ; elapsed = 00:04:27 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 748 ; free virtual = 22809
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 13a34b95a
Time (s): cpu = 00:05:29 ; elapsed = 00:04:27 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 746 ; free virtual = 22807
Ending Placer Task | Checksum: f20f1a18
Time (s): cpu = 00:05:29 ; elapsed = 00:04:27 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 746 ; free virtual = 22807
37 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:05:32 ; elapsed = 00:04:28 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 746 ; free virtual = 22807
# report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
# report_utilization -file digilent_arty_a7_utilization_place.rpt
# report_io -file digilent_arty_a7_io.rpt
report_io: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 742 ; free virtual = 22804
# report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 741 ; free virtual = 22802
# report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 97ba79a2 ConstDB: 0 ShapeSum: 5a54a076 RouteDB: 0
Post Restoration Checksum: NetGraph: 7d127a5a | NumContArr: 8dab823b | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2900ff1cf
Time (s): cpu = 00:01:27 ; elapsed = 00:01:14 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 730 ; free virtual = 22791
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2900ff1cf
Time (s): cpu = 00:01:27 ; elapsed = 00:01:14 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 730 ; free virtual = 22791
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2900ff1cf
Time (s): cpu = 00:01:27 ; elapsed = 00:01:14 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 730 ; free virtual = 22791
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2b85280db
Time (s): cpu = 00:01:39 ; elapsed = 00:01:20 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 698 ; free virtual = 22760
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.674 | TNS=-64.868| WHS=-0.771 | THS=-399.349|
Router Utilization Summary
Global Vertical Routing Utilization = 0.012926 %
Global Horizontal Routing Utilization = 0.0130719 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 3957
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 3921
Number of Partially Routed Nets = 36
Number of Node Overlaps = 38
Phase 2 Router Initialization | Checksum: 2da67e448
Time (s): cpu = 00:01:44 ; elapsed = 00:01:23 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 681 ; free virtual = 22742
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2da67e448
Time (s): cpu = 00:01:44 ; elapsed = 00:01:23 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 680 ; free virtual = 22741
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 19bb9376f
Time (s): cpu = 00:01:59 ; elapsed = 00:01:28 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 607 ; free virtual = 22669
Phase 3 Initial Routing | Checksum: 19bb9376f
Time (s): cpu = 00:01:59 ; elapsed = 00:01:28 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 607 ; free virtual = 22669
INFO: [Route 35-580] Design has 57 pins with tight setup and hold constraints.
The top 5 pins with tight setup and hold constraints:
+====================+===================+==========================================================+
| Launch Setup Clock | Launch Hold Clock | Pin |
+====================+===================+==========================================================+
| sys_clk_pin | sys_clk_pin | mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg/DIADI[3] |
| sys_clk_pin | sys_clk_pin | mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg/DIADI[5] |
| sys_clk_pin | sys_clk_pin | mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg/DIADI[14] |
| sys_clk_pin | sys_clk_pin | mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg/DIADI[26] |
| sys_clk_pin | sys_clk_pin | mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg/DIADI[21] |
+--------------------+-------------------+----------------------------------------------------------+
File with complete list of pins: tight_setup_hold_pins.txt
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 688
Number of Nodes with overlaps = 64
Number of Nodes with overlaps = 26
Number of Nodes with overlaps = 13
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.787 | TNS=-341.645| WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 307c9cf26
Time (s): cpu = 00:02:33 ; elapsed = 00:01:56 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 592 ; free virtual = 22653
Phase 4.2 Global Iteration 1
Number of Nodes with overlaps = 145
Number of Nodes with overlaps = 27
Number of Nodes with overlaps = 13
Number of Nodes with overlaps = 7
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.639 | TNS=-356.223| WHS=N/A | THS=N/A |
Phase 4.2 Global Iteration 1 | Checksum: 2ff2ab7e2
Time (s): cpu = 00:03:56 ; elapsed = 00:03:17 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 592 ; free virtual = 22654
Phase 4.3 Global Iteration 2
Number of Nodes with overlaps = 139
Number of Nodes with overlaps = 46
Number of Nodes with overlaps = 31
Number of Nodes with overlaps = 28
Number of Nodes with overlaps = 24
Number of Nodes with overlaps = 16
Number of Nodes with overlaps = 13
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.475 | TNS=-333.902| WHS=N/A | THS=N/A |
Phase 4.3 Global Iteration 2 | Checksum: 2a5bed705
Time (s): cpu = 00:04:16 ; elapsed = 00:03:34 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 585 ; free virtual = 22647
Phase 4.4 Global Iteration 3
Number of Nodes with overlaps = 41
Number of Nodes with overlaps = 16
Number of Nodes with overlaps = 20
Number of Nodes with overlaps = 19
Number of Nodes with overlaps = 7
Number of Nodes with overlaps = 7
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 13
Number of Nodes with overlaps = 7
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.456 | TNS=-340.857| WHS=N/A | THS=N/A |
Phase 4.4 Global Iteration 3 | Checksum: 1acc952d2
Time (s): cpu = 00:09:06 ; elapsed = 00:08:22 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 564 ; free virtual = 22629
Phase 4 Rip-up And Reroute | Checksum: 1acc952d2
Time (s): cpu = 00:09:06 ; elapsed = 00:08:22 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 564 ; free virtual = 22629
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 289c367c8
Time (s): cpu = 00:09:08 ; elapsed = 00:08:23 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 564 ; free virtual = 22629
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.360 | TNS=-332.495| WHS=N/A | THS=N/A |
Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 310017113
Time (s): cpu = 00:09:10 ; elapsed = 00:08:24 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 571 ; free virtual = 22635
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 310017113
Time (s): cpu = 00:09:10 ; elapsed = 00:08:24 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 571 ; free virtual = 22636
Phase 5 Delay and Skew Optimization | Checksum: 310017113
Time (s): cpu = 00:09:10 ; elapsed = 00:08:24 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 571 ; free virtual = 22636
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 288a0b19a
Time (s): cpu = 00:09:13 ; elapsed = 00:08:26 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 564 ; free virtual = 22629
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.360 | TNS=-308.465| WHS=0.056 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 249162e47
Time (s): cpu = 00:09:13 ; elapsed = 00:08:26 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 564 ; free virtual = 22629
Phase 6 Post Hold Fix | Checksum: 249162e47
Time (s): cpu = 00:09:13 ; elapsed = 00:08:26 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 564 ; free virtual = 22629
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 1.2738 %
Global Horizontal Routing Utilization = 1.61921 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
--GLOBAL Congestion:
Utilization threshold used for congestion level computation: 0.85
Congestion Report
North Dir 1x1 Area, Max Cong = 80.1802%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 47.7477%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 63.2353%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 72.0588%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: 249162e47
Time (s): cpu = 00:09:13 ; elapsed = 00:08:26 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 564 ; free virtual = 22629
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 249162e47
Time (s): cpu = 00:09:13 ; elapsed = 00:08:26 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 564 ; free virtual = 22629
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 24b2d62e8
Time (s): cpu = 00:09:15 ; elapsed = 00:08:28 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 562 ; free virtual = 22626
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=-2.360 | TNS=-308.465| WHS=0.056 | THS=0.000 |
WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 10 Post Router Timing | Checksum: 24b2d62e8
Time (s): cpu = 00:09:18 ; elapsed = 00:08:29 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 569 ; free virtual = 22634
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 12bed2734
Time (s): cpu = 00:09:18 ; elapsed = 00:08:29 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 568 ; free virtual = 22633
Ending Routing Task | Checksum: 12bed2734
Time (s): cpu = 00:09:18 ; elapsed = 00:08:30 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 568 ; free virtual = 22633
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
16 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:09:22 ; elapsed = 00:08:32 . Memory (MB): peak = 2989.164 ; gain = 0.000 ; free physical = 563 ; free virtual = 22628
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (0)
------------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (1)
-------------------------------
There is 1 port with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
-2.338 -307.826 571 14332 0.055 0.000 0 14332 3.750 0.000 0 2615
Timing constraints are not met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sck {0.000 50.000} 100.000 10.000
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin -2.338 -307.826 571 14332 0.055 0.000 0 14332 3.750 0.000 0 2615
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_arty_a7_route_status.rpt
# report_drc -file digilent_arty_a7_drc.rpt
Command: report_drc -file digilent_arty_a7_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/mriscv/mriscv/digilent_arty_a7_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_arty_a7_power.rpt
Command: report_power -file digilent_arty_a7_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "digilent_arty_a7_100t.bit"
Command: write_bitstream -force digilent_arty_a7_100t.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_arty_a7_100t.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 3173.809 ; gain = 169.648 ; free physical = 351 ; free virtual = 22420
# exit
INFO: [Common 17-206] Exiting Vivado at Sat Apr 5 00:52:10 2025...
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
[Pipeline] dir
Running in /var/jenkins_home/workspace/mriscv/mriscv
[Pipeline] {
[Pipeline] echo
Flashing FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p mriscv -b digilent_arty_a7_100t -l
Final configuration file generated at /var/jenkins_home/workspace/mriscv/mriscv/build_digilent_arty_a7_100t.tcl
Makefile executed successfully.
Makefile output:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit
empty
Jtag frequency : requested 10.00MHz -> real 10.00MHz
Open file DONE
Parse file DONE
load program
Load SRAM: [================ ] 31.00%
Load SRAM: [================================ ] 63.00%
Load SRAM: [================================================ ] 95.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
[Pipeline] echo
Testing FPGA digilent_arty_a7_100t.
[Pipeline] dir
Running in /var/jenkins_home/workspace/mriscv/mriscv
[Pipeline] {
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyUSB1
Test for FPGA in /dev/ttyUSB1
[Pipeline] sh
+ python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1
Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'}
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: b798a797-c512-46a9-875b-b156ae9c5812
hudson.AbortException: No test report files were found. Configuration error?
at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
at hudson.FilePath.act(FilePath.java:1234)
at hudson.FilePath.act(FilePath.java:1217)
at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49)
at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
at java.base/java.lang.Thread.run(Unknown Source)
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: No test report files were found. Configuration error?
Finished: FAILURE
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