Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/mmRISC-1
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf *.xml
[Pipeline] sh
+ rm -rf mmRISC-1
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/munetomo-maruyama/mmRISC-1 mmRISC-1
Cloning into 'mmRISC-1'...
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Updating files: 100% (3924/3924), done.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/mmRISC-1/mmRISC-1
[Pipeline] {
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s CPU_TOP -I verilog/common/ verilog/cpu/cpu_csr.v verilog/cpu/cpu_csr_dbg.v verilog/cpu/cpu_csr_int.v verilog/cpu/cpu_datapath.v verilog/cpu/cpu_debug.v verilog/cpu/cpu_fetch.v verilog/cpu/cpu_fpu32.v verilog/cpu/cpu_pipeline.v verilog/cpu/cpu_top.v
verilog/cpu/cpu_csr_dbg.v:470: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_csr_dbg.v:499: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_csr_dbg.v:601: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_csr_dbg.v:626: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_csr_dbg.v:638: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_csr_dbg.v:785: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_csr_dbg.v:785: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_csr_dbg.v:811: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_csr_dbg.v:811: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_csr_dbg.v:849: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_csr_dbg.v:849: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_csr_dbg.v:864: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_csr_dbg.v:890: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_csr_dbg.v:912: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_datapath.v:480: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_datapath.v:479: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:197: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:212: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:227: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:261: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:289: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:303: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:399: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:414: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:429: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:457: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:491: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:552: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:552: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:624: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:624: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:663: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_debug.v:725: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_fetch.v:377: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_fetch.v:387: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_fpu32.v:2098: error: Variable declaration in unnamed block requires SystemVerilog.
verilog/cpu/cpu_fpu32.v:2211: error: Variable declaration in unnamed block requires SystemVerilog.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
Stage "Utilities" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
Stage "digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
Stage "digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
Stage "digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
Stage "digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_arty_a7_100t
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 37
Finished: FAILURE