Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/maestro
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf maestro
[Pipeline] sh
+ git clone --recursive https://github.com/Artoriuz/maestro maestro
Cloning into 'maestro'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/maestro/maestro
[Pipeline] {
[Pipeline] sh
+ ghdl -a --std=08 Project/Components/ALU.vhd Project/Components/EX_MEM_DIV.vhd Project/Components/ID_EX_DIV.vhd Project/Components/IF_ID_DIV.vhd Project/Components/MEM_WB_DIV.vhd Project/Components/adder.vhd Project/Components/controller.vhd Project/Components/datapath.vhd Project/Components/flushing_unit.vhd Project/Components/forwarding_unit.vhd Project/Components/jump_target_unit.vhd Project/Components/mux_2_1.vhd Project/Components/mux_32_1.vhd Project/Components/mux_3_1.vhd Project/Components/mux_5_1.vhd Project/Components/progmem_interface.vhd Project/Components/program_counter.vhd Project/Components/reg1b.vhd Project/Components/reg2b.vhd Project/Components/reg32b.vhd Project/Components/reg32b_falling_edge.vhd Project/Components/reg3b.vhd Project/Components/reg4b.vhd Project/Components/reg5b.vhd Project/Components/register_file.vhd
Project/Components/EX_MEM_DIV.vhd:89:26: no declaration for "reg3b"
Project/Components/EX_MEM_DIV.vhd:89:26: component name expected
Project/Components/EX_MEM_DIV.vhd:90:28: no declaration for "reg1b"
Project/Components/EX_MEM_DIV.vhd:90:28: component name expected
Project/Components/EX_MEM_DIV.vhd:91:24: no declaration for "reg1b"
Project/Components/EX_MEM_DIV.vhd:91:24: component name expected
Project/Components/EX_MEM_DIV.vhd:94:23: no declaration for "reg2b"
Project/Components/EX_MEM_DIV.vhd:94:23: component name expected
Project/Components/EX_MEM_DIV.vhd:95:29: no declaration for "reg1b"
Project/Components/EX_MEM_DIV.vhd:95:29: component name expected
Project/Components/EX_MEM_DIV.vhd:96:37: no declaration for "reg5b"
Project/Components/EX_MEM_DIV.vhd:96:37: component name expected
Project/Components/EX_MEM_DIV.vhd:99:25: no declaration for "reg32b"
Project/Components/EX_MEM_DIV.vhd:99:25: component name expected
Project/Components/EX_MEM_DIV.vhd:100:37: no declaration for "reg32b"
Project/Components/EX_MEM_DIV.vhd:100:37: component name expected
Project/Components/EX_MEM_DIV.vhd:101:33: no declaration for "reg1b"
Project/Components/EX_MEM_DIV.vhd:101:33: component name expected
Project/Components/EX_MEM_DIV.vhd:102:34: no declaration for "reg32b"
Project/Components/EX_MEM_DIV.vhd:102:34: component name expected
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/maestro/maestro
[Pipeline] {
[Pipeline] sh
+ rm -rf LICENSE Project Quartus README.md fibonacci.txt images papers
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE