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Start of Pipeline - (14 min in block)
node - (14 min in block)
node block - (27 sec in block)
stage - (5.9 sec in block)Git Clone
stage block (Git Clone) - (5.4 sec in block)
sh - (0.75 sec in self)rm -rf maestro
sh - (4.1 sec in self)git clone --recursive https://github.com/Artoriuz/maestro maestro
stage - (2.1 sec in block)Simulation
stage block (Simulation) - (1.4 sec in block)
dir - (0.99 sec in block)maestro
dir block - (0.69 sec in block)
sh - (0.48 sec in self)ghdl -a --std=08 Project/Components/ALU.vhd Project/Components/EX_MEM_DIV.vhd Project/Components/ID_EX_DIV.vhd Project/Components/IF_ID_DIV.vhd Project/Components/MEM_WB_DIV.vhd Project/Components/adder.vhd Project/Components/controller.vhd Project/Components/datapath.vhd Project/Components/flushing_unit.vhd Project/Components/forwarding_unit.vhd Project/Components/jump_target_unit.vhd Project/Components/mux_2_1.vhd Project/Components/mux_32_1.vhd Project/Components/mux_3_1.vhd Project/Components/mux_5_1.vhd Project/Components/progmem_interface.vhd Project/Components/program_counter.vhd Project/Components/reg1b.vhd Project/Components/reg2b.vhd Project/Components/reg32b.vhd Project/Components/reg32b_falling_edge.vhd Project/Components/reg3b.vhd Project/Components/reg4b.vhd Project/Components/reg5b.vhd Project/Components/register_file.vhd
stage - (15 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (14 sec in block)
getContext - (0.29 sec in self)
parallel - (13 sec in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (11 sec in block)colorlight_i9
stage block (colorlight_i9) - (10 sec in block)
getContext - (0.68 sec in self)
stage - (1.9 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (0.7 sec in block)
getContext - (0.2 sec in self)
stage - (3.7 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (2.4 sec in block)
getContext - (0.17 sec in self)
stage - (2.6 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (1.3 sec in block)
getContext - (0.37 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (12 sec in block)
stage - (11 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (10 sec in block)
getContext - (0.67 sec in self)
stage - (1.9 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (0.82 sec in block)
getContext - (0.18 sec in self)
stage - (4 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (2.1 sec in block)
getContext - (0.18 sec in self)
stage - (2.5 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (1.5 sec in block)
getContext - (0.35 sec in self)
stage - (2.9 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (2.4 sec in block)
dir - (1.4 sec in block)maestro
dir block - (0.96 sec in block)
sh - (0.56 sec in self)rm -rf *