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Start of Pipeline - (2 min 1 sec in block)
node - (2 min 0 sec in block)
node block - (15 sec in block)
stage - (5.1 sec in block)Git Clone
stage block (Git Clone) - (4.6 sec in block)
sh - (0.59 sec in self)rm -rf *.xml
sh - (0.9 sec in self)rm -rf lizard
sh - (2.7 sec in self)git clone --recursive --depth=1 https://github.com/cornell-brg/lizard lizard
stage - (2 sec in block)Simulation
stage block (Simulation) - (1.4 sec in block)
dir - (0.97 sec in block)lizard
dir block - (0.67 sec in block)
sh - (0.47 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s asic/designs/GcdUnit-demo.v
stage - (0.98 sec in block)Utilities
stage block (Utilities) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (5.7 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5.1 sec in block)
getContext - (0.27 sec in self)
parallel - (4.4 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4.1 sec in block)
stage - (3.6 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3.3 sec in block)
getContext - (0.38 sec in self)
stage - (0.96 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.39 sec in block)
getContext - (0.17 sec in self)
stage - (0.96 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.7 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.39 sec in block)
getContext - (0.17 sec in self)
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.52 sec in block)
junit - (0.27 sec in self)**/*.xml