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[Pipeline] sh
+ rm -rf *.xml
[Pipeline] sh
+ rm -rf kronos
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/SonalPinto/kronos kronos
Cloning into 'kronos'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/kronos/kronos
[Pipeline] {
[Pipeline] echo
simulation not supported for System Verilog files
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/kronos/kronos
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/kronos/kronos -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
Trying to read file: /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_core.sv
Cache-related signals in fifo.sv
Cache-related signals in kronos_csr.sv
Cache-related signals in kronos_IF.sv
Cache-related signals in kronos_counter64.sv
Cache-related signals in kronos_RF.sv
Cache-related signals in kronos_EX.sv
Cache-related signals in kronos_ID_unit_test.sv
Cache-related signals in krz_sysbus_unit_test.sv
Results saved to /jenkins/processor_ci_utils/labels/kronos.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
Resource [digilent_arty_a7_100t] did not exist. Created.
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/kronos/kronos
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p kronos -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/kronos/kronos/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Makefile executed successfully.
Makefile output:
Building the Design...
/eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/kronos/kronos/build_digilent_arty_a7_100t.tcl
****** Vivado v2023.2 (64-bit)
**** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source /var/jenkins_home/workspace/kronos/kronos/build_digilent_arty_a7_100t.tcl
# read_verilog -sv /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_EX.sv
read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1277.664 ; gain = 24.836 ; free physical = 157 ; free virtual = 25748
# read_verilog -sv /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv
# read_verilog -sv /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_IF.sv
# read_verilog -sv /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_RF.sv
# read_verilog -sv /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_agu.sv
# read_verilog -sv /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_alu.sv
# read_verilog -sv /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_branch.sv
# read_verilog -sv /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_core.sv
# read_verilog -sv /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_counter64.sv
# read_verilog -sv /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_csr.sv
# read_verilog -sv /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_hcu.sv
# read_verilog -sv /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_lsu.sv
# read_verilog -sv /var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv
# read_verilog -sv /eda/processor_ci/rtl/kronos.sv
# read_verilog -sv /eda/processor-ci-controller/modules/uart.sv
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
# read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv
# set_param general.maxThreads 16
# read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
# set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
# synth_design -top "processorci_top" -part "xc7a100tcsg324-1"
Command: synth_design -top processorci_top -part xc7a100tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 282776
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2032.238 ; gain = 403.629 ; free physical = 162 ; free virtual = 24676
---------------------------------------------------------------------------------
WARNING: [Synth 8-11067] parameter 'INSTR_LOAD' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:41]
WARNING: [Synth 8-11067] parameter 'INSTR_STORE' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:42]
WARNING: [Synth 8-11067] parameter 'INSTR_BR' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:43]
WARNING: [Synth 8-11067] parameter 'INSTR_JALR' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:45]
WARNING: [Synth 8-11067] parameter 'INSTR_MISC' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:47]
WARNING: [Synth 8-11067] parameter 'INSTR_JAL' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:48]
WARNING: [Synth 8-11067] parameter 'INSTR_OPIMM' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:50]
WARNING: [Synth 8-11067] parameter 'INSTR_OP' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:51]
WARNING: [Synth 8-11067] parameter 'INSTR_SYS' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:52]
WARNING: [Synth 8-11067] parameter 'INSTR_AUIPC' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:54]
WARNING: [Synth 8-11067] parameter 'INSTR_LUI' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:55]
WARNING: [Synth 8-11067] parameter 'ADD' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:59]
WARNING: [Synth 8-11067] parameter 'SUB' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:60]
WARNING: [Synth 8-11067] parameter 'SLT' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:61]
WARNING: [Synth 8-11067] parameter 'SLTU' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:62]
WARNING: [Synth 8-11067] parameter 'XOR' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:63]
WARNING: [Synth 8-11067] parameter 'OR' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:64]
WARNING: [Synth 8-11067] parameter 'AND' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:65]
WARNING: [Synth 8-11067] parameter 'SLL' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:66]
WARNING: [Synth 8-11067] parameter 'SRL' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:67]
WARNING: [Synth 8-11067] parameter 'SRA' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:68]
WARNING: [Synth 8-11067] parameter 'BEQ' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:72]
WARNING: [Synth 8-11067] parameter 'BNE' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:73]
WARNING: [Synth 8-11067] parameter 'BLT' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:74]
WARNING: [Synth 8-11067] parameter 'BGE' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:75]
WARNING: [Synth 8-11067] parameter 'BLTU' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:76]
WARNING: [Synth 8-11067] parameter 'BGEU' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:77]
WARNING: [Synth 8-11067] parameter 'EQ' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:79]
WARNING: [Synth 8-11067] parameter 'LT' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:80]
WARNING: [Synth 8-11067] parameter 'GT' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:81]
WARNING: [Synth 8-11067] parameter 'BYTE' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:85]
WARNING: [Synth 8-11067] parameter 'HALF' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:86]
WARNING: [Synth 8-11067] parameter 'WORD' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:87]
WARNING: [Synth 8-11067] parameter 'ECALL' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:91]
WARNING: [Synth 8-11067] parameter 'EBREAK' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:92]
WARNING: [Synth 8-11067] parameter 'MRET' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:93]
WARNING: [Synth 8-11067] parameter 'WFI' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:94]
WARNING: [Synth 8-11067] parameter 'ZERO' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:98]
WARNING: [Synth 8-11067] parameter 'FOUR' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:99]
WARNING: [Synth 8-11067] parameter 'SOFTWARE_INTERRUPT' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:103]
WARNING: [Synth 8-11067] parameter 'TIMER_INTERRUPT' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:104]
WARNING: [Synth 8-11067] parameter 'EXTERNAL_INTERRUPT' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:105]
WARNING: [Synth 8-11067] parameter 'INSTR_ADDR_MISALIGNED' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:109]
WARNING: [Synth 8-11067] parameter 'ILLEGAL_INSTR' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:110]
WARNING: [Synth 8-11067] parameter 'BREAKPOINT' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:111]
WARNING: [Synth 8-11067] parameter 'LOAD_ADDR_MISALIGNED' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:112]
WARNING: [Synth 8-11067] parameter 'STORE_ADDR_MISALIGNED' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:113]
WARNING: [Synth 8-11067] parameter 'ECALL_MACHINE' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:114]
WARNING: [Synth 8-11067] parameter 'CSR_RW' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:120]
WARNING: [Synth 8-11067] parameter 'CSR_RS' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:121]
WARNING: [Synth 8-11067] parameter 'CSR_RC' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:122]
WARNING: [Synth 8-11067] parameter 'MSTATUS' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:125]
WARNING: [Synth 8-11067] parameter 'MIE' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:126]
WARNING: [Synth 8-11067] parameter 'MTVEC' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:127]
WARNING: [Synth 8-11067] parameter 'MSCRATCH' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:129]
WARNING: [Synth 8-11067] parameter 'MEPC' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:130]
WARNING: [Synth 8-11067] parameter 'MCAUSE' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:131]
WARNING: [Synth 8-11067] parameter 'MTVAL' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:132]
WARNING: [Synth 8-11067] parameter 'MIP' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:133]
WARNING: [Synth 8-11067] parameter 'MCYCLE' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:135]
WARNING: [Synth 8-11067] parameter 'MINSTRET' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:136]
WARNING: [Synth 8-11067] parameter 'MCYCLEH' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:137]
WARNING: [Synth 8-11067] parameter 'MINSTRETH' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:138]
WARNING: [Synth 8-11067] parameter 'PRIVILEGE_MACHINE' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:141]
WARNING: [Synth 8-11067] parameter 'DIRECT_MODE' declared inside package 'kronos_types' shall be treated as localparam [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_types.sv:143]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16]
INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/kronos.sv:6]
INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
Parameter ID bound to: 1095914585 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 8192 - type: integer
INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/rtl/clk_divider.sv:1]
Parameter COUNTER_BITS bound to: 32 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/rtl/clk_divider.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/rtl/interpreter.sv:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter ID bound to: 1095914585 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/rtl/interpreter.sv:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:66]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:125]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:199]
INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.sv:199]
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/rtl/fifo.sv:1]
Parameter DEPTH bound to: 8 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/rtl/fifo.sv:1]
INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/rtl/memory.sv:1]
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 8192 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Memory__parameterized0' [/eda/processor-ci-controller/rtl/memory.sv:1]
Parameter MEMORY_SIZE bound to: 4096 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Memory__parameterized0' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/rtl/controller.sv:1]
INFO: [Synth 8-6157] synthesizing module 'kronos_core' [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_core.sv:9]
Parameter BOOT_ADDR bound to: 0 - type: integer
Parameter FAST_BRANCH bound to: 1'b1
Parameter EN_COUNTERS bound to: 1'b1
Parameter EN_COUNTERS64B bound to: 1'b1
Parameter CATCH_ILLEGAL_INSTR bound to: 1'b1
Parameter CATCH_MISALIGNED_JMP bound to: 1'b1
Parameter CATCH_MISALIGNED_LDST bound to: 1'b1
INFO: [Synth 8-6157] synthesizing module 'kronos_IF' [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_IF.sv:25]
Parameter BOOT_ADDR bound to: 0 - type: integer
Parameter FAST_BRANCH bound to: 1'b1
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_IF.sv:104]
INFO: [Synth 8-6157] synthesizing module 'kronos_RF' [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_RF.sv:12]
INFO: [Synth 8-6155] done synthesizing module 'kronos_RF' (0#1) [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_RF.sv:12]
INFO: [Synth 8-6155] done synthesizing module 'kronos_IF' (0#1) [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_IF.sv:25]
INFO: [Synth 8-6157] synthesizing module 'kronos_ID' [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:14]
Parameter CATCH_ILLEGAL_INSTR bound to: 1'b1
Parameter CATCH_MISALIGNED_JMP bound to: 1'b1
Parameter CATCH_MISALIGNED_LDST bound to: 1'b1
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:161]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:190]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:205]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:220]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:289]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:305]
INFO: [Synth 8-6157] synthesizing module 'kronos_agu' [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_agu.sv:9]
Parameter CATCH_MISALIGNED_JMP bound to: 1'b1
Parameter CATCH_MISALIGNED_LDST bound to: 1'b1
INFO: [Synth 8-6155] done synthesizing module 'kronos_agu' (0#1) [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_agu.sv:9]
INFO: [Synth 8-6157] synthesizing module 'kronos_branch' [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_branch.sv:8]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_branch.sv:25]
INFO: [Synth 8-6155] done synthesizing module 'kronos_branch' (0#1) [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_branch.sv:8]
INFO: [Synth 8-6157] synthesizing module 'kronos_hcu' [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_hcu.sv:11]
INFO: [Synth 8-6155] done synthesizing module 'kronos_hcu' (0#1) [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_hcu.sv:11]
INFO: [Synth 8-6155] done synthesizing module 'kronos_ID' (0#1) [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:14]
INFO: [Synth 8-6157] synthesizing module 'kronos_EX' [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_EX.sv:8]
Parameter BOOT_ADDR bound to: 0 - type: integer
Parameter EN_COUNTERS bound to: 1'b1
Parameter EN_COUNTERS64B bound to: 1'b1
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_EX.sv:91]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_EX.sv:96]
INFO: [Synth 8-6157] synthesizing module 'kronos_alu' [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_alu.sv:31]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_alu.sv:135]
INFO: [Synth 8-6155] done synthesizing module 'kronos_alu' (0#1) [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_alu.sv:31]
INFO: [Synth 8-6157] synthesizing module 'kronos_lsu' [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_lsu.sv:14]
INFO: [Synth 8-6155] done synthesizing module 'kronos_lsu' (0#1) [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_lsu.sv:14]
INFO: [Synth 8-6157] synthesizing module 'kronos_csr' [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_csr.sv:29]
Parameter BOOT_ADDR bound to: 0 - type: integer
Parameter EN_COUNTERS bound to: 1'b1
Parameter EN_COUNTERS64B bound to: 1'b1
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_csr.sv:133]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_csr.sv:188]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_csr.sv:249]
INFO: [Synth 8-6157] synthesizing module 'kronos_counter64' [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_counter64.sv:12]
Parameter EN_COUNTERS bound to: 1'b1
Parameter EN_COUNTERS64B bound to: 1'b1
INFO: [Synth 8-6155] done synthesizing module 'kronos_counter64' (0#1) [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_counter64.sv:12]
INFO: [Synth 8-6155] done synthesizing module 'kronos_csr' (0#1) [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_csr.sv:29]
INFO: [Synth 8-6155] done synthesizing module 'kronos_EX' (0#1) [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_EX.sv:8]
INFO: [Synth 8-6155] done synthesizing module 'kronos_core' (0#1) [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_core.sv:9]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/rtl/reset.sv:1]
Parameter CYCLES bound to: 32'sb00000000000000000000000000010100
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/rtl/reset.sv:32]
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/rtl/reset.sv:1]
WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/kronos.sv:189]
WARNING: [Synth 8-7071] port 'rst_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/kronos.sv:189]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/kronos.sv:189]
INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/kronos.sv:6]
WARNING: [Synth 8-3848] Net intr_o in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:25]
WARNING: [Synth 8-7137] Register immediate_reg in module kronos_RF has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_RF.sv:161]
WARNING: [Synth 8-7137] Register regrd_rs1_reg in module kronos_RF has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_RF.sv:163]
WARNING: [Synth 8-7137] Register regrd_rs2_reg in module kronos_RF has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_RF.sv:167]
WARNING: [Synth 8-7137] Register regrd_rs1_en_reg in module kronos_RF has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_RF.sv:171]
WARNING: [Synth 8-7137] Register regrd_rs2_en_reg in module kronos_RF has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_RF.sv:172]
WARNING: [Synth 8-7137] Register reg_rs1_reg in module kronos_RF has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_RF.sv:174]
WARNING: [Synth 8-7137] Register reg_rs2_reg in module kronos_RF has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_RF.sv:175]
WARNING: [Synth 8-7137] Register fetch_reg[pc] in module kronos_IF has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_IF.sv:136]
WARNING: [Synth 8-7137] Register fetch_reg[ir] in module kronos_IF has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_IF.sv:136]
WARNING: [Synth 8-7137] Register skid_buffer_reg in module kronos_IF has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_IF.sv:143]
WARNING: [Synth 8-7137] Register rpend_reg in module kronos_hcu has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_hcu.sv:69]
WARNING: [Synth 8-7137] Register decode_reg[pc] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[ir] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[op1] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[op2] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[addr] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[basic] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[aluop] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[regwr_alu] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[jump] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[branch] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[load] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[store] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[mask] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[csr] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[system] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[sysop] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[illegal] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[misaligned_jmp] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register decode_reg[misaligned_ldst] in module kronos_ID has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_ID.sv:404]
WARNING: [Synth 8-7137] Register trap_handle_reg in module kronos_csr has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_csr.sv:174]
WARNING: [Synth 8-7137] Register mscratch_reg in module kronos_csr has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_csr.sv:271]
WARNING: [Synth 8-7137] Register mepc_reg in module kronos_csr has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_csr.sv:275]
WARNING: [Synth 8-7137] Register mcause_reg in module kronos_csr has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_csr.sv:278]
WARNING: [Synth 8-7137] Register mtval_reg in module kronos_csr has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_csr.sv:281]
WARNING: [Synth 8-7137] Register core_interrupt_cause_reg in module kronos_csr has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_csr.sv:322]
WARNING: [Synth 8-7137] Register regwr_sel_reg in module kronos_EX has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_EX.sv:168]
WARNING: [Synth 8-7137] Register regwr_data_reg in module kronos_EX has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/var/jenkins_home/workspace/kronos/kronos/rtl/core/kronos_EX.sv:173]
WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/kronos.sv:26]
WARNING: [Synth 8-3848] Net core_cyc in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/kronos.sv:38]
WARNING: [Synth 8-3848] Net core_we in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/kronos.sv:40]
WARNING: [Synth 8-3848] Net core_data_out in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/kronos.sv:42]
WARNING: [Synth 8-3848] Net data_mem_cyc in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/kronos.sv:47]
WARNING: [Synth 8-7129] Port decode[pc][1] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[pc][0] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[ir][6] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[ir][5] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[ir][4] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[ir][3] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[ir][2] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[ir][1] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[ir][0] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][31] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][30] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][29] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][28] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][27] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][26] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][25] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][24] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][23] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][22] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][21] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][20] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][19] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][18] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][17] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][16] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][15] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][14] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][13] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][12] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][11] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][10] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][9] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][8] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][7] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][6] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][5] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][4] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][3] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][2] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][1] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[op2][0] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][31] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][30] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][29] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][28] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][27] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][26] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][25] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][24] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][23] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][22] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][21] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][20] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][19] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][18] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][17] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][16] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][15] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][14] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][13] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][12] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][11] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][10] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][9] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][8] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][7] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][6] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][5] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][4] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][3] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][2] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][1] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[addr][0] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[basic] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[aluop][3] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[aluop][2] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[aluop][1] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[aluop][0] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[regwr_alu] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[jump] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[branch] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[load] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[store] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[mask][3] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[mask][2] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[mask][1] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[mask][0] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[system] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[sysop][1] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[sysop][0] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[illegal] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[misaligned_jmp] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[misaligned_ldst] in module kronos_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[pc][31] in module kronos_lsu is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[pc][30] in module kronos_lsu is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[pc][29] in module kronos_lsu is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[pc][28] in module kronos_lsu is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[pc][27] in module kronos_lsu is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[pc][26] in module kronos_lsu is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode[pc][25] in module kronos_lsu is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2130.207 ; gain = 501.598 ; free physical = 155 ; free virtual = 24556
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2148.020 ; gain = 519.410 ; free physical = 150 ; free virtual = 24548
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2148.020 ; gain = 519.410 ; free physical = 150 ; free virtual = 24548
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2148.020 ; gain = 0.000 ; free physical = 155 ; free virtual = 24545
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2292.801 ; gain = 0.000 ; free physical = 150 ; free virtual = 24531
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2292.836 ; gain = 0.000 ; free physical = 152 ; free virtual = 24533
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 168 ; free virtual = 24528
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 167 ; free virtual = 24527
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 164 ; free virtual = 24525
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'tx_read_fifo_state_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'kronos_IF'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'kronos_csr'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'kronos_EX'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
READ | 001 | 0001
COPY_READ_BUFFER | 010 | 0100
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
COPY_WRITE_BUFFER | 001 | 0100
WRITE | 010 | 0101
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
TX_FIFO_IDLE | 0001 | 00
TX_FIFO_READ_FIFO | 0010 | 01
TX_FIFO_WRITE_TX | 0100 | 10
TX_FIFO_WAIT | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_read_fifo_state_reg' using encoding 'one-hot' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
INIT | 00 | 00
FETCH | 01 | 01
MISS | 11 | 10
STALL | 10 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'kronos_IF'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 010 | 00
READ | 100 | 01
WRITE | 001 | 10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'kronos_csr'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
STEADY | 0000010 | 000
RETURN | 0000100 | 100
WFINTR | 0010000 | 101
TRAP | 0001000 | 011
JUMP | 0000001 | 110
LSU | 1000000 | 001
CSR | 0100000 | 010
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'kronos_EX'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
INIT | 001 | 00
RESET_COUNTER | 010 | 01
IDLE | 100 | 10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 160 ; free virtual = 24521
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 2
3 Input 33 Bit Adders := 1
2 Input 32 Bit Adders := 6
2 Input 24 Bit Adders := 2
2 Input 10 Bit Adders := 2
2 Input 8 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 6
2 Input 3 Bit Adders := 2
+---XORs :
2 Input 32 Bit XORs := 1
+---Registers :
64 Bit Registers := 2
32 Bit Registers := 33
30 Bit Registers := 1
24 Bit Registers := 4
10 Bit Registers := 2
8 Bit Registers := 11
6 Bit Registers := 1
5 Bit Registers := 4
4 Bit Registers := 9
3 Bit Registers := 2
2 Bit Registers := 3
1 Bit Registers := 58
+---RAMs :
64K Bit (2048 X 32 bit) RAMs := 1
32K Bit (1024 X 32 bit) RAMs := 1
1024 Bit (32 X 32 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
4 Input 64 Bit Muxes := 1
2 Input 64 Bit Muxes := 1
48 Input 64 Bit Muxes := 2
5 Input 32 Bit Muxes := 2
2 Input 32 Bit Muxes := 55
4 Input 32 Bit Muxes := 2
12 Input 32 Bit Muxes := 3
6 Input 32 Bit Muxes := 1
13 Input 32 Bit Muxes := 1
48 Input 24 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
48 Input 8 Bit Muxes := 2
2 Input 8 Bit Muxes := 5
4 Input 8 Bit Muxes := 4
24 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 2
14 Input 7 Bit Muxes := 1
2 Input 6 Bit Muxes := 1
3 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 10
4 Input 4 Bit Muxes := 1
13 Input 4 Bit Muxes := 1
5 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 4
2 Input 3 Bit Muxes := 6
3 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 18
48 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 7
10 Input 2 Bit Muxes := 1
20 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 101
48 Input 1 Bit Muxes := 22
3 Input 1 Bit Muxes := 9
4 Input 1 Bit Muxes := 6
5 Input 1 Bit Muxes := 13
14 Input 1 Bit Muxes := 1
15 Input 1 Bit Muxes := 1
8 Input 1 Bit Muxes := 4
12 Input 1 Bit Muxes := 1
9 Input 1 Bit Muxes := 4
7 Input 1 Bit Muxes := 2
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-3332] Sequential element (u_ex/FSM_onehot_state_reg[6]) is unused and will be removed from module kronos_core.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:25 ; elapsed = 00:01:27 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 174 ; free virtual = 24507
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1 | LUT |
|Interpreter | memory_mux_selector | 256x1 | LUT |
+------------+---------------------+---------------+----------------+
Distributed RAM: Preliminary Mapping Report (see note below)
+-------------+-----------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+-------------+-----------------------------+-----------+----------------------+------------------+
|u_Controller | Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|u_Controller | Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|u_Controller | Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 |
|u_Controller | Core_Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+-------------+-----------------------------+-----------+----------------------+------------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:36 ; elapsed = 00:01:38 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 171 ; free virtual = 24505
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:37 ; elapsed = 00:01:39 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 170 ; free virtual = 24504
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+-------------+-----------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+-------------+-----------------------------+-----------+----------------------+------------------+
|u_Controller | Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|u_Controller | Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|u_Controller | Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 |
|u_Controller | Core_Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+-------------+-----------------------------+-----------+----------------------+------------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:40 ; elapsed = 00:01:41 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 172 ; free virtual = 24505
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:01:49 ; elapsed = 00:01:50 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 172 ; free virtual = 24506
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:01:49 ; elapsed = 00:01:50 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 172 ; free virtual = 24506
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:49 ; elapsed = 00:01:51 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 173 ; free virtual = 24506
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:01:49 ; elapsed = 00:01:51 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 173 ; free virtual = 24506
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:50 ; elapsed = 00:01:51 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 173 ; free virtual = 24506
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:50 ; elapsed = 00:01:51 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 173 ; free virtual = 24506
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 3|
|2 |CARRY4 | 99|
|3 |LUT1 | 39|
|4 |LUT2 | 274|
|5 |LUT3 | 376|
|6 |LUT4 | 101|
|7 |LUT5 | 177|
|8 |LUT6 | 323|
|9 |MUXF7 | 11|
|10 |RAM256X1S | 384|
|11 |RAM32M | 2|
|12 |RAM32X1D | 4|
|13 |FDCE | 168|
|14 |FDPE | 2|
|15 |FDRE | 749|
|16 |FDSE | 4|
|17 |IBUF | 2|
|18 |OBUF | 1|
|19 |OBUFT | 2|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:50 ; elapsed = 00:01:51 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 173 ; free virtual = 24506
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 243 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:44 ; elapsed = 00:01:46 . Memory (MB): peak = 2292.836 ; gain = 519.410 ; free physical = 173 ; free virtual = 24506
Synthesis Optimization Complete : Time (s): cpu = 00:01:50 ; elapsed = 00:01:51 . Memory (MB): peak = 2292.836 ; gain = 664.227 ; free physical = 173 ; free virtual = 24506
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2292.836 ; gain = 0.000 ; free physical = 506 ; free virtual = 24839
INFO: [Netlist 29-17] Analyzing 500 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2356.832 ; gain = 0.000 ; free physical = 513 ; free virtual = 24846
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 390 instances were transformed.
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 384 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 87c77589
INFO: [Common 17-83] Releasing license: Synthesis
99 Infos, 218 Warnings, 2 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:02:08 ; elapsed = 00:02:04 . Memory (MB): peak = 2356.867 ; gain = 1079.203 ; free physical = 513 ; free virtual = 24846
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2106.990; main = 1762.258; forked = 487.254
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3275.207; main = 2356.836; forked = 1014.418
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2420.863 ; gain = 63.996 ; free physical = 509 ; free virtual = 24843
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 22a7b31e6
Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2525.676 ; gain = 104.812 ; free physical = 454 ; free virtual = 24788
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 22a7b31e6
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2770.613 ; gain = 0.000 ; free physical = 184 ; free virtual = 24518
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 22a7b31e6
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2770.613 ; gain = 0.000 ; free physical = 184 ; free virtual = 24518
Phase 1 Initialization | Checksum: 22a7b31e6
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2770.613 ; gain = 0.000 ; free physical = 184 ; free virtual = 24518
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 22a7b31e6
Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2770.613 ; gain = 0.000 ; free physical = 177 ; free virtual = 24511
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 22a7b31e6
Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2770.613 ; gain = 0.000 ; free physical = 180 ; free virtual = 24514
Phase 2 Timer Update And Timing Data Collection | Checksum: 22a7b31e6
Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2770.613 ; gain = 0.000 ; free physical = 180 ; free virtual = 24514
Phase 3 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 22a7b31e6
Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2770.613 ; gain = 0.000 ; free physical = 184 ; free virtual = 24518
Retarget | Checksum: 22a7b31e6
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 1a2c9d981
Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2770.613 ; gain = 0.000 ; free physical = 186 ; free virtual = 24520
Constant propagation | Checksum: 1a2c9d981
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 23c34bf7a
Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2770.613 ; gain = 0.000 ; free physical = 186 ; free virtual = 24520
Sweep | Checksum: 23c34bf7a
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 23c34bf7a
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2802.629 ; gain = 32.016 ; free physical = 184 ; free virtual = 24518
BUFG optimization | Checksum: 23c34bf7a
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 23c34bf7a
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.78 . Memory (MB): peak = 2802.629 ; gain = 32.016 ; free physical = 184 ; free virtual = 24517
Shift Register Optimization | Checksum: 23c34bf7a
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 23c34bf7a
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2802.629 ; gain = 32.016 ; free physical = 180 ; free virtual = 24514
Post Processing Netlist | Checksum: 23c34bf7a
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 19d04ddc3
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.96 . Memory (MB): peak = 2802.629 ; gain = 32.016 ; free physical = 177 ; free virtual = 24510
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2802.629 ; gain = 0.000 ; free physical = 177 ; free virtual = 24510
Phase 9.2 Verifying Netlist Connectivity | Checksum: 19d04ddc3
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.98 . Memory (MB): peak = 2802.629 ; gain = 32.016 ; free physical = 177 ; free virtual = 24510
Phase 9 Finalization | Checksum: 19d04ddc3
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.98 . Memory (MB): peak = 2802.629 ; gain = 32.016 ; free physical = 177 ; free virtual = 24510
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 1 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 19d04ddc3
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.99 . Memory (MB): peak = 2802.629 ; gain = 32.016 ; free physical = 177 ; free virtual = 24510
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.629 ; gain = 0.000 ; free physical = 176 ; free virtual = 24510
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 19d04ddc3
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2802.629 ; gain = 0.000 ; free physical = 186 ; free virtual = 24520
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 19d04ddc3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.629 ; gain = 0.000 ; free physical = 186 ; free virtual = 24520
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.629 ; gain = 0.000 ; free physical = 186 ; free virtual = 24520
Ending Netlist Obfuscation Task | Checksum: 19d04ddc3
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.629 ; gain = 0.000 ; free physical = 186 ; free virtual = 24520
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 2802.629 ; gain = 445.762 ; free physical = 186 ; free virtual = 24520
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2834.645 ; gain = 0.000 ; free physical = 186 ; free virtual = 24520
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c58f5e8f
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2834.645 ; gain = 0.000 ; free physical = 186 ; free virtual = 24520
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2834.645 ; gain = 0.000 ; free physical = 186 ; free virtual = 24520
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 249fb8ef
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2834.645 ; gain = 0.000 ; free physical = 187 ; free virtual = 24520
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 9d9902b4
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.672 ; gain = 7.027 ; free physical = 187 ; free virtual = 24520
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 9d9902b4
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.672 ; gain = 7.027 ; free physical = 187 ; free virtual = 24520
Phase 1 Placer Initialization | Checksum: 9d9902b4
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.672 ; gain = 7.027 ; free physical = 187 ; free virtual = 24520
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 9d2751af
Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.672 ; gain = 7.027 ; free physical = 184 ; free virtual = 24518
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 7755c671
Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.672 ; gain = 7.027 ; free physical = 184 ; free virtual = 24518
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 7755c671
Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.672 ; gain = 7.027 ; free physical = 184 ; free virtual = 24518
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: a8dbf2dc
Time (s): cpu = 00:00:23 ; elapsed = 00:00:12 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 174 ; free virtual = 24508
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 136 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 66 nets or LUTs. Breaked 0 LUT, combined 66 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2865.684 ; gain = 0.000 ; free physical = 175 ; free virtual = 24509
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 66 | 66 | 0 | 1 | 00:00:02 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 66 | 66 | 0 | 4 | 00:00:02 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 15f94d96d
Time (s): cpu = 00:00:25 ; elapsed = 00:00:15 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 175 ; free virtual = 24509
Phase 2.4 Global Placement Core | Checksum: 12e0b1195
Time (s): cpu = 00:00:36 ; elapsed = 00:00:18 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 176 ; free virtual = 24510
Phase 2 Global Placement | Checksum: 12e0b1195
Time (s): cpu = 00:00:36 ; elapsed = 00:00:18 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 176 ; free virtual = 24510
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1d55f3ed9
Time (s): cpu = 00:00:36 ; elapsed = 00:00:19 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 171 ; free virtual = 24505
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18fac8e66
Time (s): cpu = 00:00:37 ; elapsed = 00:00:20 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 175 ; free virtual = 24509
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 24ee21b22
Time (s): cpu = 00:00:37 ; elapsed = 00:00:20 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 175 ; free virtual = 24509
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 229fdbf56
Time (s): cpu = 00:00:37 ; elapsed = 00:00:20 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 173 ; free virtual = 24507
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 21066b91b
Time (s): cpu = 00:00:39 ; elapsed = 00:00:21 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 168 ; free virtual = 24502
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 24f4732a8
Time (s): cpu = 00:00:39 ; elapsed = 00:00:22 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 178 ; free virtual = 24512
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 27a235664
Time (s): cpu = 00:00:39 ; elapsed = 00:00:22 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 178 ; free virtual = 24512
Phase 3 Detail Placement | Checksum: 27a235664
Time (s): cpu = 00:00:39 ; elapsed = 00:00:22 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 178 ; free virtual = 24512
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1b2d59b42
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.875 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 216b92cc6
Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2865.684 ; gain = 0.000 ; free physical = 170 ; free virtual = 24504
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 216b92cc6
Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2865.684 ; gain = 0.000 ; free physical = 160 ; free virtual = 24494
Phase 4.1.1.1 BUFG Insertion | Checksum: 1b2d59b42
Time (s): cpu = 00:00:46 ; elapsed = 00:00:25 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 155 ; free virtual = 24489
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.875. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 17992f4c7
Time (s): cpu = 00:00:46 ; elapsed = 00:00:25 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 175 ; free virtual = 24509
Time (s): cpu = 00:00:46 ; elapsed = 00:00:25 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 175 ; free virtual = 24509
Phase 4.1 Post Commit Optimization | Checksum: 17992f4c7
Time (s): cpu = 00:00:46 ; elapsed = 00:00:26 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 175 ; free virtual = 24509
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 17992f4c7
Time (s): cpu = 00:00:47 ; elapsed = 00:00:26 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 175 ; free virtual = 24509
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 1x1|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 17992f4c7
Time (s): cpu = 00:00:47 ; elapsed = 00:00:26 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 175 ; free virtual = 24509
Phase 4.3 Placer Reporting | Checksum: 17992f4c7
Time (s): cpu = 00:00:47 ; elapsed = 00:00:26 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 175 ; free virtual = 24509
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2865.684 ; gain = 0.000 ; free physical = 175 ; free virtual = 24509
Time (s): cpu = 00:00:47 ; elapsed = 00:00:26 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 175 ; free virtual = 24509
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f042fd76
Time (s): cpu = 00:00:47 ; elapsed = 00:00:26 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 175 ; free virtual = 24509
Ending Placer Task | Checksum: 1b5f3b641
Time (s): cpu = 00:00:47 ; elapsed = 00:00:26 . Memory (MB): peak = 2865.684 ; gain = 31.039 ; free physical = 175 ; free virtual = 24509
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:27 . Memory (MB): peak = 2865.684 ; gain = 63.055 ; free physical = 175 ; free virtual = 24509
# report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
# report_utilization -file digilent_arty_a7_utilization_place.rpt
# report_io -file digilent_arty_a7_io.rpt
report_io: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2865.684 ; gain = 0.000 ; free physical = 175 ; free virtual = 24509
# report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2865.684 ; gain = 0.000 ; free physical = 175 ; free virtual = 24509
# report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: dfbe6d36 ConstDB: 0 ShapeSum: d635490b RouteDB: 0
Post Restoration Checksum: NetGraph: ed88d7a7 | NumContArr: d2f30e41 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 345cddb22
Time (s): cpu = 00:01:27 ; elapsed = 00:01:13 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 155 ; free virtual = 24483
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 345cddb22
Time (s): cpu = 00:01:27 ; elapsed = 00:01:13 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 153 ; free virtual = 24481
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 345cddb22
Time (s): cpu = 00:01:27 ; elapsed = 00:01:14 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 152 ; free virtual = 24480
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2b0eb894a
Time (s): cpu = 00:01:35 ; elapsed = 00:01:17 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24473
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.008 | THS=0.000 |
Router Utilization Summary
Global Vertical Routing Utilization = 0.00526614 %
Global Horizontal Routing Utilization = 0.00440466 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 2133
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 2096
Number of Partially Routed Nets = 37
Number of Node Overlaps = 25
Phase 2 Router Initialization | Checksum: 3442b4a6f
Time (s): cpu = 00:01:38 ; elapsed = 00:01:19 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 171 ; free virtual = 24470
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 3442b4a6f
Time (s): cpu = 00:01:38 ; elapsed = 00:01:19 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 171 ; free virtual = 24470
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 2af30c6e9
Time (s): cpu = 00:01:41 ; elapsed = 00:01:20 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 171 ; free virtual = 24469
Phase 3 Initial Routing | Checksum: 2af30c6e9
Time (s): cpu = 00:01:41 ; elapsed = 00:01:20 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 171 ; free virtual = 24469
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 97
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.528 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 19239330d
Time (s): cpu = 00:01:45 ; elapsed = 00:01:22 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
Phase 4 Rip-up And Reroute | Checksum: 19239330d
Time (s): cpu = 00:01:45 ; elapsed = 00:01:22 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 19239330d
Time (s): cpu = 00:01:45 ; elapsed = 00:01:22 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 19239330d
Time (s): cpu = 00:01:45 ; elapsed = 00:01:22 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
Phase 5 Delay and Skew Optimization | Checksum: 19239330d
Time (s): cpu = 00:01:45 ; elapsed = 00:01:22 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 15a020f4e
Time (s): cpu = 00:01:45 ; elapsed = 00:01:23 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.624 | TNS=0.000 | WHS=0.376 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 15a020f4e
Time (s): cpu = 00:01:45 ; elapsed = 00:01:23 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
Phase 6 Post Hold Fix | Checksum: 15a020f4e
Time (s): cpu = 00:01:45 ; elapsed = 00:01:23 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.608391 %
Global Horizontal Routing Utilization = 0.692953 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 15a020f4e
Time (s): cpu = 00:01:46 ; elapsed = 00:01:23 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 15a020f4e
Time (s): cpu = 00:01:46 ; elapsed = 00:01:23 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1bc6f31e7
Time (s): cpu = 00:01:47 ; elapsed = 00:01:24 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.624 | TNS=0.000 | WHS=0.376 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1bc6f31e7
Time (s): cpu = 00:01:47 ; elapsed = 00:01:24 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 1e3cc9f1d
Time (s): cpu = 00:01:47 ; elapsed = 00:01:24 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
Ending Routing Task | Checksum: 1e3cc9f1d
Time (s): cpu = 00:01:47 ; elapsed = 00:01:24 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 175 ; free virtual = 24464
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:51 ; elapsed = 00:01:27 . Memory (MB): peak = 2897.699 ; gain = 0.000 ; free physical = 172 ; free virtual = 24461
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (10738)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (17885)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (10738)
----------------------------
There are 2482 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[0]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[10]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[11]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[12]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[13]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[14]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[15]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[16]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[17]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[18]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[19]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[1]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[20]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[21]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[22]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[23]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[24]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[25]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[26]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[27]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[28]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[29]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[2]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[30]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[31]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[3]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[4]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[5]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[6]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[7]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[8]/Q (HIGH)
There are 258 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[9]/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (17885)
----------------------------------------------------
There are 17885 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (1)
-------------------------------
There is 1 port with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.649 0.000 0 1 0.392 0.000 0 1 4.500 0.000 0 2
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sck {0.000 50.000} 100.000 10.000
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.649 0.000 0 1 0.392 0.000 0 1 4.500 0.000 0 2
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_arty_a7_route_status.rpt
# report_drc -file digilent_arty_a7_drc.rpt
Command: report_drc -file digilent_arty_a7_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/kronos/kronos/digilent_arty_a7_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_arty_a7_power.rpt
Command: report_power -file digilent_arty_a7_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "digilent_arty_a7_100t.bit"
Command: write_bitstream -force digilent_arty_a7_100t.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_arty_a7_100t.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 3155.867 ; gain = 240.238 ; free physical = 167 ; free virtual = 24132
# exit
INFO: [Common 17-206] Exiting Vivado at Thu Apr 10 02:41:30 2025...
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
[Pipeline] dir
Running in /var/jenkins_home/workspace/kronos/kronos
[Pipeline] {
[Pipeline] echo
Flashing FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p kronos -b digilent_arty_a7_100t -l
Makefile executed successfully.
Makefile output:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit
empty
Jtag frequency : requested 10.00MHz -> real 10.00MHz
Open file DONE
Parse file DONE
load program
Load SRAM: [================ ] 31.00%
Load SRAM: [================================ ] 63.00%
Load SRAM: [================================================ ] 95.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
[Pipeline] echo
Testing FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyUSB1
Test for FPGA in /dev/ttyUSB1
[Pipeline] sh
+ python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459
32
Connected to FPGA with ID: b'ARTY'
Checking for sync keyword...
Sync keyword matched.
Testsuite configurated.
Running tests: RV32I in /eda/processor_ci_tests/tests/RV32I
Running basic tests in /eda/processor_ci_tests/tests/RV32I/basic, with breakpoint 60
Running test: 000-addi.hex
Running test: 001-sw.hex
Running test: 002-slti.hex
Running test: 003-sltiu.hex
Running test: 004-xori.hex
Running test: 005-ori.hex
Running test: 006-andi.hex
Running test: 007-slli.hex
Running test: 008-srli.hex
Running test: 009-srai.hex
Running test: 010-lui.hex
Running test: 011-auipc.hex
Running test: 012-jal.hex
Running test: 013-jalr.hex
Running test: 014-beq.hex
Running test: 015-bne.hex
Running test: 016-blt.hex
Running test: 017-bge.hex
Running test: 018-bltu.hex
Running test: 019-bgeu.hex
Running test: 020-lb.hex
Running test: 021-lh.hex
Running test: 022-lw.hex
Running test: 023-lbu.hex
Running test: 024-lhu.hex
Running test: 025-sb.hex
Running test: 026-sh.hex
Running test: 027-add.hex
Running test: 028-sub.hex
Running test: 029-sll.hex
Running test: 030-slt.hex
Running test: 031-sltu.hex
Running test: 032-xor.hex
Running test: 033-srl.hex
Running test: 034-sra.hex
Running test: 035-or.hex
Running test: 036-and.hex
Running test: 037-fence.hex
Running test: 038-ecall.hex
Running test: 039-ebreak.hex
Running test: 040-timeout.hex
Running test: 041-forwarding.hex
Running test: 042-forwarding-lw.hex
JUnit XML report generated: test_results_1744267304.1563063.xml
All tests finished.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: UNSTABLE
![[Jenkins]](/jenkins/static/d05f6cb3/images/svgs/logo.svg){kind=logo}
