Console Output

+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p kronos -b digilent_arty_a7_100t
Final configuration file generated at /var/jenkins_home/workspace/kronos/kronos/build_digilent_arty_a7_100t.tcl
Error executing Makefile.
ERROR: [DRC LUTLP-1] Combinatorial Loop Alert: 2 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is kronos_core_inst/u_id/data_ack. Please evaluate your design. The cells in the loop are: kronos_core_inst/u_id/FSM_sequential_state[1]_i_6, and kronos_core_inst/u_id/memory_reg_0_255_0_0_i_12__0.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 307, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.