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Start of Pipeline - (9 min 20 sec in block)
node - (9 min 19 sec in block)
node block - (15 sec in block)
stage - (4.8 sec in block)Git Clone
stage block (Git Clone) - (3.9 sec in block)
sh - (1.2 sec in self)rm -rf *.xml
sh - (0.69 sec in self)rm -rf kant-v
sh - (1 sec in self)git clone --recursive --depth=1 https://github.com/viniciuskant/kant-v kant-v
stage - (2.2 sec in block)Simulation
stage block (Simulation) - (1.5 sec in block)
dir - (1 sec in block)kant-v
dir block - (0.71 sec in block)
sh - (0.49 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s src/alu.v src/control.v src/registers.v
stage - (0.98 sec in block)Utilities
stage block (Utilities) - (0.37 sec in block)
getContext - (0.15 sec in self)
stage - (5.8 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5.2 sec in block)
getContext - (0.27 sec in self)
parallel - (4.6 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4.2 sec in block)
stage - (3.7 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3.4 sec in block)
getContext - (0.4 sec in self)
stage - (0.95 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.37 sec in block)
getContext - (0.17 sec in self)
stage - (0.97 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.39 sec in block)
getContext - (0.17 sec in self)
stage - (0.72 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.41 sec in block)
getContext - (0.19 sec in self)
stage - (0.77 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.51 sec in block)
junit - (0.25 sec in self)**/*.xml