Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s src/alu.v src/control.v src/registers.v
error: Unable to find the root module "src/alu.v" in the Verilog source.
     : Perhaps ``-s src/alu.v'' is incorrect?
1 error(s) during elaboration.