Console Output

+ iverilog -o simulation.out -g2012 -s ibex_core rtl/ibex_alu.sv rtl/ibex_branch_predict.sv rtl/ibex_compressed_decoder.sv rtl/ibex_controller.sv rtl/ibex_core.sv rtl/ibex_counter.sv rtl/ibex_cs_registers.sv rtl/ibex_csr.sv rtl/ibex_decoder.sv rtl/ibex_dummy_instr.sv rtl/ibex_ex_block.sv rtl/ibex_fetch_fifo.sv rtl/ibex_icache.sv rtl/ibex_id_stage.sv rtl/ibex_if_stage.sv rtl/ibex_load_store_unit.sv rtl/ibex_lockstep.sv rtl/ibex_multdiv_fast.sv rtl/ibex_multdiv_slow.sv rtl/ibex_pkg.sv rtl/ibex_pmp.sv rtl/ibex_prefetch_buffer.sv rtl/ibex_register_file_ff.sv rtl/ibex_register_file_fpga.sv rtl/ibex_register_file_latch.sv rtl/ibex_top.sv rtl/ibex_top_tracing.sv rtl/ibex_tracer.sv rtl/ibex_tracer_pkg.sv rtl/ibex_wb_stage.sv
rtl/ibex_branch_predict.sv:19: Include file prim_assert.sv not found
rtl/ibex_alu.sv:10: syntax error
I give up.