Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s CPU -I src/ src/ALU.v src/CPU.v src/Encoders.v src/ImmediateExtractor.v src/RAM.v src/ROM.v src/RegFile.v
src//ALU.v:1: error: 'ALU' has already been declared in this scope.
src/ALU.v:1:      : It was declared here as a module.
src//ALU.v:37: error: Module ALU was already declared here: src/ALU.v:1

src/Encoders.v:1: error: 'Encoder_4' has already been declared in this scope.
src//Encoders.v:1:      : It was declared here as a module.
src/Encoders.v:19: error: Module Encoder_4 was already declared here: src//Encoders.v:1

src/Encoders.v:21: error: 'Encoder_8' has already been declared in this scope.
src//Encoders.v:21:      : It was declared here as a module.
src/Encoders.v:44: error: Module Encoder_8 was already declared here: src//Encoders.v:21

src/Encoders.v:46: error: 'Encoder_16' has already been declared in this scope.
src//Encoders.v:46:      : It was declared here as a module.
src/Encoders.v:77: error: Module Encoder_16 was already declared here: src//Encoders.v:46

src/ImmediateExtractor.v:1: error: 'ImmediateExtractor' has already been declared in this scope.
src//ImmediateExtractor.v:1:      : It was declared here as a module.
src/ImmediateExtractor.v:36: error: Module ImmediateExtractor was already declared here: src//ImmediateExtractor.v:1

src/RAM.v:12: syntax error
src/RAM.v:12: error: Incomprehensible for loop.
src/RegFile.v:1: error: 'RegFile' has already been declared in this scope.
src//RegFile.v:1:      : It was declared here as a module.
src/RegFile.v:36: error: Module RegFile was already declared here: src//RegFile.v:1