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Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/e203_hbirdv2
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf e203_hbirdv2
[Pipeline] sh
+ git clone --recursive https://github.com/riscv-mcu/e203_hbirdv2 e203_hbirdv2
Cloning into 'e203_hbirdv2'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2
[Pipeline] {
[Pipeline] sh
+ iverilog -o simulation.out -g2009 -DDISABLE_SV_ASSERTION=1 -gsupported-assertions -s e203_cpu_top -I rtl/e203/core/ rtl/e203/core/config.v rtl/e203/core/e203_biu.v rtl/e203/core/e203_clk_ctrl.v rtl/e203/core/e203_clkgate.v rtl/e203/core/e203_core.v rtl/e203/core/e203_cpu.v rtl/e203/core/e203_cpu_top.v rtl/e203/core/e203_defines.v rtl/e203/core/e203_dtcm_ctrl.v rtl/e203/core/e203_dtcm_ram.v rtl/e203/core/e203_extend_csr.v rtl/e203/core/e203_exu.v rtl/e203/core/e203_exu_alu.v rtl/e203/core/e203_exu_alu_bjp.v rtl/e203/core/e203_exu_alu_csrctrl.v rtl/e203/core/e203_exu_alu_dpath.v rtl/e203/core/e203_exu_alu_lsuagu.v rtl/e203/core/e203_exu_alu_muldiv.v rtl/e203/core/e203_exu_alu_rglr.v rtl/e203/core/e203_exu_branchslv.v rtl/e203/core/e203_exu_commit.v rtl/e203/core/e203_exu_csr.v rtl/e203/core/e203_exu_decode.v rtl/e203/core/e203_exu_disp.v rtl/e203/core/e203_exu_excp.v rtl/e203/core/e203_exu_longpwbck.v rtl/e203/core/e203_exu_nice.v rtl/e203/core/e203_exu_oitf.v rtl/e203/core/e203_exu_regfile.v rtl/e203/core/e203_exu_wbck.v rtl/e203/core/e203_ifu.v rtl/e203/core/e203_ifu_ifetch.v rtl/e203/core/e203_ifu_ift2icb.v rtl/e203/core/e203_ifu_litebpu.v rtl/e203/core/e203_ifu_minidec.v rtl/e203/core/e203_irq_sync.v rtl/e203/core/e203_itcm_ctrl.v rtl/e203/core/e203_itcm_ram.v rtl/e203/core/e203_lsu.v rtl/e203/core/e203_lsu_ctrl.v rtl/e203/core/e203_reset_ctrl.v rtl/e203/core/e203_srams.v rtl/e203/general/sirv_1cyc_sram_ctrl.v rtl/e203/general/sirv_gnrl_bufs.v rtl/e203/general/sirv_gnrl_dffs.v rtl/e203/general/sirv_gnrl_icbs.v rtl/e203/general/sirv_gnrl_ram.v rtl/e203/general/sirv_gnrl_xchecker.v rtl/e203/general/sirv_sim_ram.v rtl/e203/general/sirv_sram_icb_ctrl.v rtl/e203/subsys/e203_subsys_clint.v rtl/e203/subsys/e203_subsys_gfcm.v rtl/e203/subsys/e203_subsys_hclkgen.v rtl/e203/subsys/e203_subsys_hclkgen_rstsync.v rtl/e203/subsys/e203_subsys_main.v rtl/e203/subsys/e203_subsys_mems.v rtl/e203/subsys/e203_subsys_nice_core.v rtl/e203/subsys/e203_subsys_perips.v rtl/e203/subsys/e203_subsys_plic.v rtl/e203/subsys/e203_subsys_pll.v rtl/e203/subsys/e203_subsys_pllclkdiv.v rtl/e203/subsys/e203_subsys_top.v
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
The resource [colorlight_i9] is locked by build biriscv #21 #21 since Oct 23, 2024, 3:12 AM.
[Resource: colorlight_i9] is not free, waiting for execution ...
[Required resources: [colorlight_i9]] added into queue at position 0
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_nexys4_ddr]
The resource [digilent_nexys4_ddr] is locked by build biriscv #21 #21 since Oct 23, 2024, 3:12 AM.
[Resource: digilent_nexys4_ddr] is not free, waiting for execution ...
[Required resources: [digilent_nexys4_ddr]] added into queue at position 1
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2
[Pipeline] {
[Pipeline] echo
Iniciando síntese para FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p e203_hbirdv2 -b colorlight_i9
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/build_colorlight_i9.tcl
Erro ao executar o Makefile.
ERROR: Can't open include file `e203_defines.v'!
make: *** [/eda/processor-ci/makefiles/colorlight_i9.mk:12: colorlight_i9.json] Error 1

Traceback (most recent call last):
  File "/eda/processor-ci/main.py", line 79, in <module>
    main(
  File "/eda/processor-ci/main.py", line 26, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor-ci/core/fpga.py", line 113, in build
    raise subprocess.CalledProcessError(process.returncode, "make")
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
Stage "Flash colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
Stage "Teste colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
Lock acquired on [Resource: digilent_nexys4_ddr]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2
[Pipeline] {
[Pipeline] echo
Iniciando síntese para FPGA digilent_nexys4_ddr.
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p e203_hbirdv2 -b digilent_nexys4_ddr
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/build_digilent_nexys4_ddr.tcl
Erro ao executar o Makefile.
ERROR: [Synth 8-9263] cannot open include file 'e203_defines.v' [/var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_clint.v:28]
ERROR: [Synth 8-9263] cannot open include file 'e203_defines.v' [/var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_gfcm.v:28]
ERROR: [Synth 8-9263] cannot open include file 'e203_defines.v' [/var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_hclkgen.v:28]
ERROR: [Synth 8-9263] cannot open include file 'e203_defines.v' [/var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_hclkgen_rstsync.v:27]
ERROR: [Synth 8-9263] cannot open include file 'e203_defines.v' [/var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_main.v:29]
ERROR: [Synth 8-9263] cannot open include file 'e203_defines.v' [/var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_mems.v:29]
ERROR: [Synth 8-9263] cannot open include file 'e203_defines.v' [/var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_nice_core.v:25]
ERROR: [Synth 8-9263] cannot open include file 'e203_defines.v' [/var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_perips.v:28]
ERROR: [Synth 8-9263] cannot open include file 'e203_defines.v' [/var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_plic.v:29]
ERROR: [Synth 8-9263] cannot open include file 'e203_defines.v' [/var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_pll.v:28]
ERROR: [Synth 8-9263] cannot open include file 'e203_defines.v' [/var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_pllclkdiv.v:28]
ERROR: [Synth 8-9263] cannot open include file 'e203_defines.v' [/var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_top.v:29]
ERROR: [Synth 8-9263] cannot open include file 'e203_defines.v' [/var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_clint.v:28]
ERROR: [Synth 8-439] module 'Controller' not found [/eda/processor-ci/rtl/e203_hbirdv2.v:48]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor-ci/rtl/e203_hbirdv2.v:1]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor-ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor-ci/main.py", line 79, in <module>
    main(
  File "/eda/processor-ci/main.py", line 26, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor-ci/core/fpga.py", line 113, in build
    raise subprocess.CalledProcessError(process.returncode, "make")
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "Flash digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "Teste digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_nexys4_ddr]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2
[Pipeline] {
[Pipeline] sh
+ rm -rf LICENSE README.md build_colorlight_i9.tcl build_digilent_nexys4_ddr.tcl doc e203_core.core e203_soc.core fpga pics riscv-tools rtl simulation.out tb vsim
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE