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Start of Pipeline - (1 min 39 sec in block)
node - (1 min 37 sec in block)
node block - (1 min 37 sec in block)
stage - (10 sec in block)Git Clone
stage block (Git Clone) - (9.9 sec in block)
sh - (0.69 sec in self)rm -rf e203_hbirdv2
sh - (8.8 sec in self)git clone --recursive https://github.com/riscv-mcu/e203_hbirdv2 e203_hbirdv2
stage - (3.4 sec in block)Simulation
stage block (Simulation) - (2.4 sec in block)
dir - (1.6 sec in block)e203_hbirdv2
dir block - (1.1 sec in block)
sh - (0.74 sec in self)
stage - (1 min 20 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (1 min 20 sec in block)
parallel - (1 min 19 sec in block)
parallel block (Branch: colorlight_i9) - (0.11 sec in block)
stage - (10 sec in block)colorlight_i9
stage block (colorlight_i9) - (10 sec in block)
lock - (9.2 sec in block)colorlight_i9
lock block - (8.3 sec in block)
stage - (4.9 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (4.2 sec in block)
dir - (3 sec in block)e203_hbirdv2
dir block - (2.6 sec in block)
echo - (0.33 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (1.5 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p e203_hbirdv2 -b colorlight_i9
stage - (0.98 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.4 sec in block)
getContext - (0.16 sec in self)
stage - (0.77 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.47 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (1 min 18 sec in block)
stage - (1 min 17 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (1 min 17 sec in block)
lock - (1 min 15 sec in block)digilent_nexys4_ddr
lock block - (1 min 14 sec in block)
stage - (1 min 11 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (1 min 10 sec in block)
dir - (1 min 9 sec in block)e203_hbirdv2
dir block - (1 min 9 sec in block)
echo - (0.33 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (1 min 8 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p e203_hbirdv2 -b digilent_nexys4_ddr
stage - (0.97 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.38 sec in block)
getContext - (0.16 sec in self)
stage - (0.69 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.38 sec in block)
getContext - (0.16 sec in self)
stage - (1.4 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.2 sec in block)
dir - (0.84 sec in block)e203_hbirdv2
dir block - (0.6 sec in block)
sh - (0.4 sec in self)rm -rf *