![[Jenkins]](/jenkins/static/d05f6cb3/images/svgs/logo.svg){kind=logo}
| Step | Arguments | Status | ||
|---|---|---|---|---|
| Start of Pipeline - (14 sec in block) | ||||
| node - (14 sec in block) | ||||
| node block - (13 sec in block) | ||||
| stage - (9.6 sec in block) | Git Clone | |||
| stage block (Git Clone) - (9.1 sec in block) | ||||
| sh - (0.52 sec in self) | rm -Rf e203_hbirdv2/ build/ | |||
| sh - (8.3 sec in self) | git clone --recurse-submodules https://github.com/riscv-mcu/e203_hbirdv2.git | |||
| stage - (3.5 sec in block) | IVerilog | |||
| stage block (IVerilog) - (3.3 sec in block) | ||||
| dir - (2.9 sec in block) | e203_hbirdv2/ | |||
| dir block - (2.6 sec in block) | ||||
| sh - (0.44 sec in self) | mkdir -p build | |||
| sh - (0.46 sec in self) | cp rtl/e203/core/e203_defines.v . | |||
| sh - (0.45 sec in self) | cp rtl/e203/core/config.v . | |||
| sh - (0.67 sec in self) | /eda/oss-cad-suite/bin/iverilog -DDISABLE_SV_ASSERTION=1 -g2009 -gsupported-assertions -o build/out.o -s e203_cpu_top rtl/e203/core/*.v rtl/e203/general/*.v rtl/e203/subsys/*.v | |||
| sh - (0.41 sec in self) | /eda/oss-cad-suite/bin/vvp build/out.o |