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Started by timer [Pipeline] Start of Pipeline [Pipeline] node Still waiting to schedule task Waiting for next available executor Running on Jenkins in /var/jenkins_home/workspace/e203_hbirdv2 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf *.xml [Pipeline] sh + rm -rf e203_hbirdv2 [Pipeline] sh + git clone --recursive --depth=1 https://github.com/riscv-mcu/e203_hbirdv2 e203_hbirdv2 Cloning into 'e203_hbirdv2'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2 [Pipeline] { [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2009 -DDISABLE_SV_ASSERTION=1 -gsupported-assertions -s e203_cpu_top -I rtl/e203/core/ rtl/e203/core/config.v rtl/e203/core/e203_biu.v rtl/e203/core/e203_clk_ctrl.v rtl/e203/core/e203_clkgate.v rtl/e203/core/e203_core.v rtl/e203/core/e203_cpu.v rtl/e203/core/e203_cpu_top.v rtl/e203/core/e203_defines.v rtl/e203/core/e203_dtcm_ctrl.v rtl/e203/core/e203_dtcm_ram.v rtl/e203/core/e203_extend_csr.v rtl/e203/core/e203_exu.v rtl/e203/core/e203_exu_alu.v rtl/e203/core/e203_exu_alu_bjp.v rtl/e203/core/e203_exu_alu_csrctrl.v rtl/e203/core/e203_exu_alu_dpath.v rtl/e203/core/e203_exu_alu_lsuagu.v rtl/e203/core/e203_exu_alu_muldiv.v rtl/e203/core/e203_exu_alu_rglr.v rtl/e203/core/e203_exu_branchslv.v rtl/e203/core/e203_exu_commit.v rtl/e203/core/e203_exu_csr.v rtl/e203/core/e203_exu_decode.v rtl/e203/core/e203_exu_disp.v rtl/e203/core/e203_exu_excp.v rtl/e203/core/e203_exu_longpwbck.v rtl/e203/core/e203_exu_nice.v rtl/e203/core/e203_exu_oitf.v rtl/e203/core/e203_exu_regfile.v rtl/e203/core/e203_exu_wbck.v rtl/e203/core/e203_ifu.v rtl/e203/core/e203_ifu_ifetch.v rtl/e203/core/e203_ifu_ift2icb.v rtl/e203/core/e203_ifu_litebpu.v rtl/e203/core/e203_ifu_minidec.v rtl/e203/core/e203_irq_sync.v rtl/e203/core/e203_itcm_ctrl.v rtl/e203/core/e203_itcm_ram.v rtl/e203/core/e203_lsu.v rtl/e203/core/e203_lsu_ctrl.v rtl/e203/core/e203_reset_ctrl.v rtl/e203/core/e203_srams.v rtl/e203/general/sirv_1cyc_sram_ctrl.v rtl/e203/general/sirv_gnrl_bufs.v rtl/e203/general/sirv_gnrl_dffs.v rtl/e203/general/sirv_gnrl_icbs.v rtl/e203/general/sirv_gnrl_ram.v rtl/e203/general/sirv_gnrl_xchecker.v rtl/e203/general/sirv_sim_ram.v rtl/e203/general/sirv_sram_icb_ctrl.v rtl/e203/subsys/e203_subsys_clint.v rtl/e203/subsys/e203_subsys_gfcm.v rtl/e203/subsys/e203_subsys_hclkgen.v rtl/e203/subsys/e203_subsys_hclkgen_rstsync.v rtl/e203/subsys/e203_subsys_main.v rtl/e203/subsys/e203_subsys_mems.v rtl/e203/subsys/e203_subsys_nice_core.v rtl/e203/subsys/e203_subsys_perips.v rtl/e203/subsys/e203_subsys_plic.v rtl/e203/subsys/e203_subsys_pll.v rtl/e203/subsys/e203_subsys_pllclkdiv.v rtl/e203/subsys/e203_subsys_top.v [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2 [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2 -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels Trying to read file: /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_cpu_top.v Trying to read file: /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/config.v Trying to read file: /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_biu.v Trying to read file: /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_clk_ctrl.v Trying to read file: /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_clkgate.v Trying to read file: /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_core.v Cache-related signals in sirv_1cyc_sram_ctrl.v Cache-related signals in sirv_gnrl_bufs.v Cache-related signals in sirv_gnrl_icbs.v Cache-related signals in sirv_sram_icb_ctrl.v Cache-related signals in sirv_tlfragmenter_qspi_1.v Cache-related signals in uart_interrupt.v Cache-related signals in spi_master_rx.v Cache-related signals in e203_exu_alu_rglr.v Cache-related signals in e203_exu_longpwbck.v Cache-related signals in e203_exu_nice.v Cache-related signals in e203_exu_alu_csrctrl.v Cache-related signals in e203_exu_alu_muldiv.v Cache-related signals in e203_exu_oitf.v Cache-related signals in e203_exu_decode.v Cache-related signals in e203_ifu_ifetch.v Cache-related signals in e203_defines.v Cache-related signals in e203_exu_excp.v Cache-related signals in e203_itcm_ctrl.v Cache-related signals in e203_ifu_ift2icb.v Cache-related signals in e203_exu_alu.v Cache-related signals in e203_lsu.v Cache-related signals in e203_dtcm_ctrl.v Cache-related signals in e203_exu_wbck.v Cache-related signals in e203_exu.v Cache-related signals in e203_core.v Cache-related signals in e203_ifu.v Cache-related signals in e203_cpu.v Cache-related signals in e203_exu_alu_bjp.v Cache-related signals in e203_lsu_ctrl.v Cache-related signals in e203_exu_disp.v Cache-related signals in e203_exu_alu_lsuagu.v Cache-related signals in sirv_mrom_top.v Cache-related signals in sirv_debug_module.v Cache-related signals in sirv_jtag_dtm.v Cache-related signals in tb_top.v Results saved to /jenkins/processor_ci_utils/labels/e203_hbirdv2.json [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] Resource [digilent_arty_a7_100t] did not exist. Created. Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2 [Pipeline] { [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p e203_hbirdv2 -b digilent_arty_a7_100t [LOCK] Criado: run.lock File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'. Final configuration file generated at /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/build_digilent_arty_a7_100t.tcl [LOCK] Removido: run.lock Makefile executed successfully. Makefile output: Building the Design... /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/build_digilent_arty_a7_100t.tcl ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/build_digilent_arty_a7_100t.tcl # read_verilog -sv /eda/processor_ci/rtl/e203_hbirdv2.sv read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1277.148 ; gain = 24.836 ; free physical = 5176 ; free virtual = 26653 # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/config.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_biu.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_clk_ctrl.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_clkgate.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_core.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_cpu.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_cpu_top.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_defines.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_dtcm_ctrl.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_dtcm_ram.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_extend_csr.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu_bjp.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu_csrctrl.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu_dpath.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu_lsuagu.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu_muldiv.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu_rglr.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_branchslv.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_commit.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_csr.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_decode.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_disp.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_excp.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_longpwbck.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_nice.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_oitf.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_regfile.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_wbck.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_ifu.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_ifu_ifetch.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_ifu_ift2icb.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_ifu_litebpu.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_ifu_minidec.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_irq_sync.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_itcm_ctrl.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_itcm_ram.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_lsu.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_lsu_ctrl.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_reset_ctrl.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_srams.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_1cyc_sram_ctrl.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_gnrl_bufs.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_gnrl_dffs.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_gnrl_icbs.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_gnrl_ram.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_gnrl_xchecker.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_sim_ram.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_sram_icb_ctrl.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_clint.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_gfcm.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_hclkgen.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_hclkgen_rstsync.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_main.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_mems.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_nice_core.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_perips.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_plic.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_pll.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_pllclkdiv.v # read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_top.v # set_property include_dirs [list "/var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/" ] [get_filesets sources_1] # read_verilog -sv /eda/processor-ci-controller/modules/uart.sv # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v # read_verilog -sv /eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv # read_verilog -sv /eda/processor-ci-controller/rtl/axi4_to_wishbone.sv # read_verilog -sv /eda/processor-ci-controller/rtl/axi4lite_to_wishbone.sv # read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv # read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv # read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv # read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv # read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv # read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv # set_param general.maxThreads 16 # read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc" # set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] # synth_design -top "processorci_top" -part "xc7a100tcsg324-1" Command: synth_design -top processorci_top -part xc7a100tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 91002 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2032.777 ; gain = 403.715 ; free physical = 4154 ; free virtual = 25631 --------------------------------------------------------------------------------- WARNING: [Synth 8-10929] literal value 'd8 truncated to fit in 3 bits [/eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv:104] WARNING: [Synth 8-10929] literal value 'd16 truncated to fit in 3 bits [/eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv:105] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16] INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/e203_hbirdv2.sv:5] INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer Parameter ID bound to: 1095914585 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 8192 - type: integer INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/rtl/clk_divider.sv:1] Parameter COUNTER_BITS bound to: 32 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/rtl/clk_divider.sv:1] INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/rtl/interpreter.sv:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter ID bound to: 1095914585 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/rtl/interpreter.sv:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:66] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:125] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:199] INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.sv:199] INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/rtl/fifo.sv:1] Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/rtl/fifo.sv:1] INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.sv:1] INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/rtl/memory.sv:1] Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 8192 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1] INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/rtl/controller.sv:1] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/rtl/reset.sv:1] Parameter CYCLES bound to: 32'sb00000000000000000000000000010100 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/rtl/reset.sv:32] INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/rtl/reset.sv:1] WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/e203_hbirdv2.sv:157] WARNING: [Synth 8-7071] port 'rst_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/e203_hbirdv2.sv:157] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/e203_hbirdv2.sv:157] INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/e203_hbirdv2.sv:5] WARNING: [Synth 8-3848] Net intr_o in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:25] WARNING: [Synth 8-3848] Net data_memory_ack in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:119] WARNING: [Synth 8-3848] Net data_memory_read_data in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:120] WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/e203_hbirdv2.sv:25] WARNING: [Synth 8-3848] Net core_cyc in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/e203_hbirdv2.sv:38] WARNING: [Synth 8-3848] Net core_stb in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/e203_hbirdv2.sv:39] WARNING: [Synth 8-3848] Net core_we in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/e203_hbirdv2.sv:40] WARNING: [Synth 8-3848] Net core_addr in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/e203_hbirdv2.sv:41] WARNING: [Synth 8-3848] Net core_data_out in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/e203_hbirdv2.sv:42] WARNING: [Synth 8-7129] Port addr_i[31] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[30] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[29] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[28] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[27] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[26] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[25] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[24] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[23] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[22] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[21] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[20] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[19] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[18] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[17] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[16] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[15] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[14] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[13] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[1] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[0] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port intr_o in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port sck_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port cs_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port mosi_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port miso_o in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rw_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rst in module processorci_top is either unconnected or has no load --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2134.715 ; gain = 505.652 ; free physical = 4037 ; free virtual = 25515 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2149.559 ; gain = 520.496 ; free physical = 4037 ; free virtual = 25515 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2149.559 ; gain = 520.496 ; free physical = 4037 ; free virtual = 25515 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2149.559 ; gain = 0.000 ; free physical = 4043 ; free virtual = 25521 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2299.309 ; gain = 0.000 ; free physical = 4018 ; free virtual = 25496 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2299.344 ; gain = 0.000 ; free physical = 4017 ; free virtual = 25496 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 4012 ; free virtual = 25490 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 4010 ; free virtual = 25488 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 4009 ; free virtual = 25487 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'tx_read_fifo_state_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 READ | 001 | 0001 COPY_READ_BUFFER | 010 | 0100 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 COPY_WRITE_BUFFER | 001 | 0100 WRITE | 010 | 0101 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- TX_FIFO_IDLE | 0001 | 00 TX_FIFO_READ_FIFO | 0010 | 01 TX_FIFO_WRITE_TX | 0100 | 10 TX_FIFO_WAIT | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_read_fifo_state_reg' using encoding 'one-hot' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- INIT | 001 | 00 RESET_COUNTER | 010 | 01 IDLE | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'ResetBootSystem' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 4007 ; free virtual = 25486 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 64 Bit Adders := 2 2 Input 32 Bit Adders := 3 2 Input 24 Bit Adders := 2 2 Input 10 Bit Adders := 2 2 Input 8 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 6 2 Input 3 Bit Adders := 2 +---Registers : 64 Bit Registers := 2 32 Bit Registers := 11 24 Bit Registers := 4 10 Bit Registers := 2 8 Bit Registers := 11 6 Bit Registers := 1 4 Bit Registers := 6 3 Bit Registers := 2 1 Bit Registers := 25 +---RAMs : 64K Bit (2048 X 32 bit) RAMs := 1 64 Bit (8 X 8 bit) RAMs := 2 +---Muxes : 4 Input 64 Bit Muxes := 1 2 Input 64 Bit Muxes := 1 48 Input 64 Bit Muxes := 2 5 Input 32 Bit Muxes := 2 2 Input 32 Bit Muxes := 6 48 Input 24 Bit Muxes := 1 48 Input 8 Bit Muxes := 2 2 Input 8 Bit Muxes := 4 24 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 2 3 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 4 5 Input 3 Bit Muxes := 4 2 Input 3 Bit Muxes := 5 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 13 48 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 4 2 Input 1 Bit Muxes := 47 48 Input 1 Bit Muxes := 22 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 3 5 Input 1 Bit Muxes := 11 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met WARNING: [Synth 8-7129] Port addr_i[31] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[30] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[29] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[28] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[27] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[26] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[25] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[24] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[23] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[22] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[21] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[20] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[19] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[18] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[17] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[16] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[15] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[14] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[13] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[1] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[0] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port intr_o in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port sck_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port cs_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port mosi_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port miso_o in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rw_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rst in module processorci_top is either unconnected or has no load --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 3976 ; free virtual = 25461 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +------------+---------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+---------------------+---------------+----------------+ |Interpreter | memory_mux_selector | 256x1 | LUT | |Interpreter | memory_mux_selector | 256x1 | LUT | +------------+---------------------+---------------+----------------+ Distributed RAM: Preliminary Mapping Report (see note below) +----------------+--------------------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +----------------+--------------------------------------+-----------+----------------------+------------------+ |processorci_top | u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |processorci_top | u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |processorci_top | u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 | +----------------+--------------------------------------+-----------+----------------------+------------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:00 ; elapsed = 00:01:01 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 3980 ; free virtual = 25465 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:01:05 ; elapsed = 00:01:06 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 3955 ; free virtual = 25441 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +----------------+--------------------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +----------------+--------------------------------------+-----------+----------------------+------------------+ |processorci_top | u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |processorci_top | u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |processorci_top | u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 | +----------------+--------------------------------------+-----------+----------------------+------------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:01:06 ; elapsed = 00:01:07 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 3974 ; free virtual = 25459 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:01:15 ; elapsed = 00:01:16 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 3965 ; free virtual = 25450 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:01:15 ; elapsed = 00:01:16 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 3965 ; free virtual = 25450 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:16 ; elapsed = 00:01:17 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 3965 ; free virtual = 25450 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:01:16 ; elapsed = 00:01:17 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 3966 ; free virtual = 25451 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:01:16 ; elapsed = 00:01:17 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 3968 ; free virtual = 25453 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:01:16 ; elapsed = 00:01:17 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 3968 ; free virtual = 25453 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 2| |2 |CARRY4 | 56| |3 |LUT1 | 36| |4 |LUT2 | 234| |5 |LUT3 | 214| |6 |LUT4 | 85| |7 |LUT5 | 96| |8 |LUT6 | 247| |9 |MUXF7 | 22| |10 |RAM256X1S | 256| |11 |RAM32M | 2| |12 |RAM32X1D | 4| |13 |FDRE | 602| |14 |FDSE | 4| |15 |IBUF | 2| |16 |OBUF | 1| |17 |OBUFT | 2| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:01:16 ; elapsed = 00:01:17 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 3968 ; free virtual = 25453 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 31 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:01:12 ; elapsed = 00:01:13 . Memory (MB): peak = 2299.344 ; gain = 520.496 ; free physical = 3965 ; free virtual = 25451 Synthesis Optimization Complete : Time (s): cpu = 00:01:16 ; elapsed = 00:01:17 . Memory (MB): peak = 2299.344 ; gain = 670.281 ; free physical = 3965 ; free virtual = 25450 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2299.344 ; gain = 0.000 ; free physical = 4236 ; free virtual = 25721 INFO: [Netlist 29-17] Analyzing 340 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2363.340 ; gain = 0.000 ; free physical = 4242 ; free virtual = 25727 INFO: [Project 1-111] Unisim Transformation Summary: A total of 262 instances were transformed. RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances Synth Design complete | Checksum: 86d9f598 INFO: [Common 17-83] Releasing license: Synthesis 52 Infos, 79 Warnings, 2 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:35 ; elapsed = 00:01:30 . Memory (MB): peak = 2363.375 ; gain = 1086.227 ; free physical = 4242 ; free virtual = 25727 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2053.017; main = 1768.336; forked = 427.547 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3237.723; main = 2363.344; forked = 970.426 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2427.371 ; gain = 63.996 ; free physical = 4248 ; free virtual = 25733 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1c5c2652d Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2523.184 ; gain = 95.812 ; free physical = 4196 ; free virtual = 25681 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 1c5c2652d Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2767.152 ; gain = 0.000 ; free physical = 3922 ; free virtual = 25408 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1c5c2652d Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2767.152 ; gain = 0.000 ; free physical = 3922 ; free virtual = 25408 Phase 1 Initialization | Checksum: 1c5c2652d Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2767.152 ; gain = 0.000 ; free physical = 3922 ; free virtual = 25408 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 1c5c2652d Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2767.152 ; gain = 0.000 ; free physical = 3923 ; free virtual = 25408 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 1c5c2652d Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2767.152 ; gain = 0.000 ; free physical = 3923 ; free virtual = 25408 Phase 2 Timer Update And Timing Data Collection | Checksum: 1c5c2652d Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2767.152 ; gain = 0.000 ; free physical = 3923 ; free virtual = 25408 Phase 3 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 1c5c2652d Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2767.152 ; gain = 0.000 ; free physical = 3923 ; free virtual = 25408 Retarget | Checksum: 1c5c2652d INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 1aeb13cc9 Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2767.152 ; gain = 0.000 ; free physical = 3923 ; free virtual = 25408 Constant propagation | Checksum: 1aeb13cc9 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 1e2a94b6f Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2767.152 ; gain = 0.000 ; free physical = 3923 ; free virtual = 25408 Sweep | Checksum: 1e2a94b6f INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 1e2a94b6f Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2799.168 ; gain = 32.016 ; free physical = 3922 ; free virtual = 25408 BUFG optimization | Checksum: 1e2a94b6f INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 1e2a94b6f Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2799.168 ; gain = 32.016 ; free physical = 3922 ; free virtual = 25408 Shift Register Optimization | Checksum: 1e2a94b6f INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 1e2a94b6f Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2799.168 ; gain = 32.016 ; free physical = 3922 ; free virtual = 25408 Post Processing Netlist | Checksum: 1e2a94b6f INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 11d2ce8c0 Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.54 . Memory (MB): peak = 2799.168 ; gain = 32.016 ; free physical = 3922 ; free virtual = 25408 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.168 ; gain = 0.000 ; free physical = 3922 ; free virtual = 25408 Phase 9.2 Verifying Netlist Connectivity | Checksum: 11d2ce8c0 Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.55 . Memory (MB): peak = 2799.168 ; gain = 32.016 ; free physical = 3922 ; free virtual = 25408 Phase 9 Finalization | Checksum: 11d2ce8c0 Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2799.168 ; gain = 32.016 ; free physical = 3922 ; free virtual = 25408 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 0 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 1 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 11d2ce8c0 Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2799.168 ; gain = 32.016 ; free physical = 3922 ; free virtual = 25408 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.168 ; gain = 0.000 ; free physical = 3922 ; free virtual = 25408 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 11d2ce8c0 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2799.168 ; gain = 0.000 ; free physical = 3922 ; free virtual = 25408 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 11d2ce8c0 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.168 ; gain = 0.000 ; free physical = 3922 ; free virtual = 25408 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.168 ; gain = 0.000 ; free physical = 3922 ; free virtual = 25408 Ending Netlist Obfuscation Task | Checksum: 11d2ce8c0 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.168 ; gain = 0.000 ; free physical = 3922 ; free virtual = 25408 INFO: [Common 17-83] Releasing license: Implementation 18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 2799.168 ; gain = 435.793 ; free physical = 3922 ; free virtual = 25408 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2831.184 ; gain = 0.000 ; free physical = 3922 ; free virtual = 25407 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: e512c24e Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2831.184 ; gain = 0.000 ; free physical = 3922 ; free virtual = 25407 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2831.184 ; gain = 0.000 ; free physical = 3921 ; free virtual = 25407 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 180d38c4e Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2831.184 ; gain = 0.000 ; free physical = 3924 ; free virtual = 25410 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 2148274ad Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2838.211 ; gain = 7.027 ; free physical = 3927 ; free virtual = 25413 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 2148274ad Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2838.211 ; gain = 7.027 ; free physical = 3926 ; free virtual = 25411 Phase 1 Placer Initialization | Checksum: 2148274ad Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2838.211 ; gain = 7.027 ; free physical = 3925 ; free virtual = 25410 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 27fa0d8f9 Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 2838.211 ; gain = 7.027 ; free physical = 3922 ; free virtual = 25408 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 244976327 Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 2838.211 ; gain = 7.027 ; free physical = 3918 ; free virtual = 25404 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 244976327 Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 2838.211 ; gain = 7.027 ; free physical = 3917 ; free virtual = 25403 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 24c2f6eac Time (s): cpu = 00:00:20 ; elapsed = 00:00:11 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3924 ; free virtual = 25410 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 103 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 49 nets or LUTs. Breaked 0 LUT, combined 49 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2846.215 ; gain = 0.000 ; free physical = 3916 ; free virtual = 25402 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 49 | 49 | 0 | 1 | 00:00:01 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 49 | 49 | 0 | 4 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1cbe35d8f Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3914 ; free virtual = 25400 Phase 2.4 Global Placement Core | Checksum: 1f9af18d4 Time (s): cpu = 00:00:28 ; elapsed = 00:00:14 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3910 ; free virtual = 25395 Phase 2 Global Placement | Checksum: 1f9af18d4 Time (s): cpu = 00:00:28 ; elapsed = 00:00:14 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3910 ; free virtual = 25395 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1f4b63aae Time (s): cpu = 00:00:28 ; elapsed = 00:00:14 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3910 ; free virtual = 25395 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 187155759 Time (s): cpu = 00:00:29 ; elapsed = 00:00:15 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3910 ; free virtual = 25395 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: f8233e74 Time (s): cpu = 00:00:29 ; elapsed = 00:00:15 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3910 ; free virtual = 25395 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 10c6978d9 Time (s): cpu = 00:00:29 ; elapsed = 00:00:15 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3910 ; free virtual = 25395 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 208bbe42e Time (s): cpu = 00:00:30 ; elapsed = 00:00:16 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3920 ; free virtual = 25405 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1eb9fb664 Time (s): cpu = 00:00:30 ; elapsed = 00:00:16 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3920 ; free virtual = 25405 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1f7d9f9eb Time (s): cpu = 00:00:30 ; elapsed = 00:00:17 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3920 ; free virtual = 25405 Phase 3 Detail Placement | Checksum: 1f7d9f9eb Time (s): cpu = 00:00:30 ; elapsed = 00:00:17 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3919 ; free virtual = 25404 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 12538eee4 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.882 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: fd077dea Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2846.215 ; gain = 0.000 ; free physical = 3918 ; free virtual = 25403 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: fd077dea Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2846.215 ; gain = 0.000 ; free physical = 3917 ; free virtual = 25403 Phase 4.1.1.1 BUFG Insertion | Checksum: 12538eee4 Time (s): cpu = 00:00:35 ; elapsed = 00:00:19 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3917 ; free virtual = 25403 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 12baba6c3 Time (s): cpu = 00:00:35 ; elapsed = 00:00:19 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3916 ; free virtual = 25401 Time (s): cpu = 00:00:35 ; elapsed = 00:00:19 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3916 ; free virtual = 25401 Phase 4.1 Post Commit Optimization | Checksum: 12baba6c3 Time (s): cpu = 00:00:35 ; elapsed = 00:00:19 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3913 ; free virtual = 25399 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 12baba6c3 Time (s): cpu = 00:00:35 ; elapsed = 00:00:19 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3908 ; free virtual = 25393 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 1x1| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 12baba6c3 Time (s): cpu = 00:00:35 ; elapsed = 00:00:19 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3910 ; free virtual = 25396 Phase 4.3 Placer Reporting | Checksum: 12baba6c3 Time (s): cpu = 00:00:35 ; elapsed = 00:00:19 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3910 ; free virtual = 25396 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2846.215 ; gain = 0.000 ; free physical = 3910 ; free virtual = 25396 Time (s): cpu = 00:00:35 ; elapsed = 00:00:19 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3910 ; free virtual = 25396 Phase 4 Post Placement Optimization and Clean-Up | Checksum: d1d89166 Time (s): cpu = 00:00:35 ; elapsed = 00:00:19 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3910 ; free virtual = 25396 Ending Placer Task | Checksum: 6b1a421b Time (s): cpu = 00:00:35 ; elapsed = 00:00:19 . Memory (MB): peak = 2846.215 ; gain = 15.031 ; free physical = 3911 ; free virtual = 25397 29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:38 ; elapsed = 00:00:20 . Memory (MB): peak = 2846.215 ; gain = 47.047 ; free physical = 3911 ; free virtual = 25397 # report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt # report_utilization -file digilent_arty_a7_utilization_place.rpt # report_io -file digilent_arty_a7_io.rpt report_io: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2846.215 ; gain = 0.000 ; free physical = 3908 ; free virtual = 25393 # report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2846.215 ; gain = 0.000 ; free physical = 3911 ; free virtual = 25397 # report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: 62db67dd ConstDB: 0 ShapeSum: 83eda3e RouteDB: 0 Post Restoration Checksum: NetGraph: d3599431 | NumContArr: 6bc0fd10 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 2c46c867b Time (s): cpu = 00:01:23 ; elapsed = 00:01:12 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3894 ; free virtual = 25380 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 2c46c867b Time (s): cpu = 00:01:23 ; elapsed = 00:01:12 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3894 ; free virtual = 25380 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 2c46c867b Time (s): cpu = 00:01:23 ; elapsed = 00:01:12 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3894 ; free virtual = 25380 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 19e4398cb Time (s): cpu = 00:01:29 ; elapsed = 00:01:15 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3878 ; free virtual = 25364 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.008 | THS=0.000 | Router Utilization Summary Global Vertical Routing Utilization = 8.70436e-05 % Global Horizontal Routing Utilization = 7.10429e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 1398 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 1397 Number of Partially Routed Nets = 1 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 20c8ced71 Time (s): cpu = 00:01:31 ; elapsed = 00:01:16 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3879 ; free virtual = 25366 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 20c8ced71 Time (s): cpu = 00:01:31 ; elapsed = 00:01:16 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3879 ; free virtual = 25366 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 251846ce9 Time (s): cpu = 00:01:33 ; elapsed = 00:01:16 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3874 ; free virtual = 25360 Phase 3 Initial Routing | Checksum: 251846ce9 Time (s): cpu = 00:01:33 ; elapsed = 00:01:16 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3873 ; free virtual = 25359 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 75 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.540 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 30002cb34 Time (s): cpu = 00:01:36 ; elapsed = 00:01:18 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25358 Phase 4 Rip-up And Reroute | Checksum: 30002cb34 Time (s): cpu = 00:01:36 ; elapsed = 00:01:18 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25358 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 30002cb34 Time (s): cpu = 00:01:36 ; elapsed = 00:01:18 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25358 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 30002cb34 Time (s): cpu = 00:01:36 ; elapsed = 00:01:18 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25358 Phase 5 Delay and Skew Optimization | Checksum: 30002cb34 Time (s): cpu = 00:01:36 ; elapsed = 00:01:18 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25358 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 2ab8a6458 Time (s): cpu = 00:01:36 ; elapsed = 00:01:19 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25358 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 2ab8a6458 Time (s): cpu = 00:01:36 ; elapsed = 00:01:19 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25358 Phase 6 Post Hold Fix | Checksum: 2ab8a6458 Time (s): cpu = 00:01:36 ; elapsed = 00:01:19 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25358 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.396396 % Global Horizontal Routing Utilization = 0.47137 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 2ab8a6458 Time (s): cpu = 00:01:36 ; elapsed = 00:01:19 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25358 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 2ab8a6458 Time (s): cpu = 00:01:36 ; elapsed = 00:01:19 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25358 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 267defb41 Time (s): cpu = 00:01:37 ; elapsed = 00:01:19 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25357 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 267defb41 Time (s): cpu = 00:01:37 ; elapsed = 00:01:19 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25357 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 640b61cc Time (s): cpu = 00:01:38 ; elapsed = 00:01:19 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25357 Ending Routing Task | Checksum: 640b61cc Time (s): cpu = 00:01:38 ; elapsed = 00:01:20 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3871 ; free virtual = 25357 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:01:40 ; elapsed = 00:01:22 . Memory (MB): peak = 2894.238 ; gain = 0.000 ; free physical = 3865 ; free virtual = 25351 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (1653) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (11977) 5. checking no_input_delay (1) 6. checking no_output_delay (1) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (1653) --------------------------- There are 1653 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH) 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (11977) ---------------------------------------------------- There are 11977 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (1) ------------------------------ There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (1) ------------------------------- There is 1 port with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sck {0.000 50.000} 100.000 10.000 sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin 8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_arty_a7_route_status.rpt # report_drc -file digilent_arty_a7_drc.rpt Command: report_drc -file digilent_arty_a7_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/digilent_arty_a7_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_arty_a7_power.rpt Command: report_power -file digilent_arty_a7_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "digilent_arty_a7_100t.bit" Command: write_bitstream -force digilent_arty_a7_100t.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./digilent_arty_a7_100t.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 3143.352 ; gain = 245.270 ; free physical = 3538 ; free virtual = 25029 # exit INFO: [Common 17-206] Exiting Vivado at Fri Apr 11 23:24:06 2025... [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) [Pipeline] dir Running in /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2 [Pipeline] { [Pipeline] echo Flashing FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p e203_hbirdv2 -b digilent_arty_a7_100t -l Makefile executed successfully. Makefile output: Flashing the FPGA... /eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit empty Jtag frequency : requested 10.00MHz -> real 10.00MHz Open file DONE Parse file DONE load program Load SRAM: [=============== ] 30.00% Load SRAM: [=============================== ] 62.00% Load SRAM: [=============================================== ] 94.00% Load SRAM: [===================================================] 100.00% Done Shift IR 35 ir: 1 isc_done 1 isc_ena 0 init 1 done 1 [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) [Pipeline] echo Testing FPGA digilent_arty_a7_100t. [Pipeline] sh + echo Test for FPGA in /dev/ttyUSB1 Test for FPGA in /dev/ttyUSB1 [Pipeline] sh + python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459 32 Connected to FPGA with ID: b'ARTY' Checking for sync keyword... Sync keyword matched. Testsuite configurated. Running tests: RV32I in /eda/processor_ci_tests/tests/RV32I Running basic tests in /eda/processor_ci_tests/tests/RV32I/basic, with breakpoint 60 Running test: 000-addi.hex Running test: 001-sw.hex Running test: 002-slti.hex Running test: 003-sltiu.hex Running test: 004-xori.hex Running test: 005-ori.hex Running test: 006-andi.hex Running test: 007-slli.hex Running test: 008-srli.hex Running test: 009-srai.hex Running test: 010-lui.hex Running test: 011-auipc.hex Running test: 012-jal.hex Running test: 013-jalr.hex Running test: 014-beq.hex Running test: 015-bne.hex Running test: 016-blt.hex Running test: 017-bge.hex Running test: 018-bltu.hex Running test: 019-bgeu.hex Running test: 020-lb.hex Running test: 021-lh.hex Running test: 022-lw.hex Running test: 023-lbu.hex Running test: 024-lhu.hex Running test: 025-sb.hex Running test: 026-sh.hex Running test: 027-add.hex Running test: 028-sub.hex Running test: 029-sll.hex Running test: 030-slt.hex Running test: 031-sltu.hex Running test: 032-xor.hex Running test: 033-srl.hex Running test: 034-sra.hex Running test: 035-or.hex Running test: 036-and.hex Running test: 037-fence.hex Running test: 038-ecall.hex Running test: 039-ebreak.hex Running test: 040-timeout.hex Running test: 041-forwarding.hex Running test: 042-forwarding-lw.hex JUnit XML report generated: test_results_1744428265.3452864.xml All tests finished. [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results [Checks API] No suitable checks publisher found. [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline Finished: UNSTABLE