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Start of Pipeline - (1 min 3 sec in block)
node - (1 min 2 sec in block)
node block - (1 min 2 sec in block)
stage - (3.8 sec in block)Git Clone
stage block (Git Clone) - (3.3 sec in block)
sh - (0.45 sec in self)rm -rf *.xml
sh - (0.46 sec in self)rm -rf cve2
sh - (2.2 sec in self)git clone --recursive --depth=1 https://github.com/openhwgroup/cve2 cve2
stage - (1.3 sec in block)Simulation
stage block (Simulation) - (0.94 sec in block)
dir - (0.56 sec in block)cve2
dir block - (0.32 sec in block)
echo - (0.11 sec in self)simulation not supported for System Verilog files
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.85 sec in block)cve2
dir block - (0.6 sec in block)
sh - (0.39 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (54 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (53 sec in block)
parallel - (53 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (52 sec in block)
stage - (52 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (51 sec in block)
lock - (51 sec in block)digilent_arty_a7_100t
lock block - (50 sec in block)
stage - (48 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (48 sec in block)
dir - (47 sec in block)cve2
dir block - (47 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (46 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p cve2 -b digilent_arty_a7_100t
stage - (1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (0.67 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.74 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.5 sec in block)
junit - (0.26 sec in self)**/*.xml