Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/cve2
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf cve2
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/openhwgroup/cve2 cve2
Cloning into 'cve2'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/cve2/cve2
[Pipeline] {
[Pipeline] echo
simulation not supported for System Verilog files
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/cve2/cve2
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/cve2/cve2 -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
Trying to read file: /var/jenkins_home/workspace/cve2/cve2/syn/rtl/cve2_clock_gating.v
Trying to read file: /var/jenkins_home/workspace/cve2/cve2/syn/rtl/cve2_clock_gating.v
Trying to read file: /var/jenkins_home/workspace/cve2/cve2/syn/rtl/latch_map.v
Trying to read file: /var/jenkins_home/workspace/cve2/cve2/syn/rtl/prim_clock_gating.v
Trying to read file: /var/jenkins_home/workspace/cve2/cve2/bhv/cve2_sim_clock_gate.sv
Trying to read file: /var/jenkins_home/workspace/cve2/cve2/dv/riscv_compliance/rtl/cve2_riscv_compliance.sv
Cache-related signals in cve2_alu.sv
Cache-related signals in cve2_compressed_decoder.sv
Cache-related signals in cve2_ex_block.sv
Cache-related signals in cve2_wb.sv
Cache-related signals in cve2_if_stage.sv
Cache-related signals in cve2_decoder.sv
Cache-related signals in cve2_load_store_unit.sv
Cache-related signals in cve2_prefetch_buffer.sv
Cache-related signals in cve2_fetch_fifo.sv
Cache-related signals in cve2_id_stage.sv
Cache-related signals in cve2_core.sv
Cache-related signals in cve2_multdiv_fast.sv
Cache-related signals in cve2_controller.sv
Cache-related signals in cve2_multdiv_slow.sv
Cache-related signals in riscv_illegal_instr.sv
Cache-related signals in riscv_instr_sequence.sv
Cache-related signals in riscv_page_table_entry.sv
Cache-related signals in riscv_reg.sv
Cache-related signals in riscv_asm_program_gen.sv
Cache-related signals in riscv_page_table_list.sv
Cache-related signals in riscv_compressed_instr.sv
Cache-related signals in riscv_instr.sv
Cache-related signals in dv_base_reg.sv
Cache-related signals in dv_base_reg_block.sv
Cache-related signals in dv_base_env_cfg.sv
Cache-related signals in csr_seq_lib.sv
Cache-related signals in prim_subreg_async.sv
Cache-related signals in prim_packer.sv
Cache-related signals in prim_arbiter_tree.sv
Cache-related signals in prim_clock_meas.sv
Cache-related signals in prim_count_pkg.sv
Cache-related signals in prim_reg_cdc.sv
Cache-related signals in prim_crc32.sv
Cache-related signals in prim_util_pkg.sv
Cache-related signals in prim_fifo_async.sv
Cache-related signals in prim_subreg_arb.sv
Cache-related signals in prim_ram_2p_async_adv.sv
Cache-related signals in prim_ram_2p_adv.sv
Cache-related signals in prim_fifo_async_sram_adapter.sv
Cache-related signals in prim_subreg.sv
Cache-related signals in prim_packer_fifo.sv
Cache-related signals in prim_count.sv
Cache-related signals in prim_max_tree.sv
Cache-related signals in prim_lfsr.sv
Cache-related signals in prim_sum_tree.sv
Cache-related signals in prim_mubi_pkg.sv
Cache-related signals in prim_ram_1p_scr.sv
Cache-related signals in prim_ram_1p_adv.sv
Cache-related signals in prim_arbiter_fixed.sv
Cache-related signals in prim_arbiter_ppc.sv
Cache-related signals in prim_fifo_sync.sv
Cache-related signals in prim_sram_arbiter.sv
Cache-related signals in prim_subreg_shadow.sv
Cache-related signals in prim_cdc_rand_delay.sv
Cache-related signals in prim_dom_and_2share.sv
Cache-related signals in prim_prince_tb.sv
Cache-related signals in prim_alert_tb.sv
Cache-related signals in prim_fifo_sync_assert_fpv.sv
Cache-related signals in prim_fifo_sync_tb.sv
Cache-related signals in prim_generic_otp.sv
Cache-related signals in timer.sv
Cache-related signals in formal_tb.sv
Cache-related signals in obi2ahbm_adapter.sv
Results saved to /jenkins/processor_ci_utils/labels/cve2.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
Resource [colorlight_i9] did not exist. Created.
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
Resource [digilent_arty_a7_100t] did not exist. Created.
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/cve2/cve2
[Pipeline] {
[Pipeline] dir
Running in /var/jenkins_home/workspace/cve2/cve2
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA colorlight_i9.
[Pipeline] sh
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p cve2 -b colorlight_i9
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p cve2 -b digilent_arty_a7_100t
Final configuration file generated at /var/jenkins_home/workspace/cve2/cve2/build_colorlight_i9.tcl
Error executing Makefile.
ERROR: Error when parsing design. Aborting!
make: *** [/eda/processor_ci/makefiles/colorlight_i9.mk:12: colorlight_i9.json] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 307, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
Stage "Flash colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test colorlight_i9)
Stage "Test colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
Final configuration file generated at /var/jenkins_home/workspace/cve2/cve2/build_digilent_arty_a7_100t.tcl
Error executing Makefile.
ERROR: [Common 17-69] Command failed: File '/eda/processor-ci-controller/modules/uart.v' does not exist
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 307, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_arty_a7_100t
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 366ec316-531c-4934-abea-b6c589c1f5e6
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE