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Start of Pipeline - (3 min 51 sec in block)
node - (3 min 49 sec in block)
node block - (45 sec in block)
stage - (33 sec in block)Git Clone
stage block (Git Clone) - (32 sec in block)
sh - (0.63 sec in self)rm -rf *.xml
sh - (0.68 sec in self)rm -rf cva6
sh - (30 sec in self)git clone --recursive --depth=1 https://github.com/openhwgroup/cva6 cva6
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.94 sec in block)
dir - (0.57 sec in block)cva6
dir block - (0.31 sec in block)
echo - (0.11 sec in self)simulation not supported for System Verilog files
stage - (3.2 sec in block)Utilities
stage block (Utilities) - (2.4 sec in block)
dir - (0.99 sec in block)cva6
dir block - (0.67 sec in block)
sh - (0.45 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (6.3 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5.8 sec in block)
getContext - (0.27 sec in self)
parallel - (5.1 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4.8 sec in block)
stage - (4.3 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (4 sec in block)
getContext - (0.38 sec in self)
stage - (0.96 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.39 sec in block)
getContext - (0.17 sec in self)
stage - (1.6 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (0.69 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.8 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.54 sec in block)
junit - (0.29 sec in self)**/*.xml