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Start of Pipeline - (6 min 3 sec in block)
node - (6 min 2 sec in block)
node block - (42 sec in block)
stage - (30 sec in block)Git Clone
stage block (Git Clone) - (29 sec in block)
sh - (0.57 sec in self)rm -rf *.xml
sh - (0.51 sec in self)rm -rf cva6
sh - (28 sec in self)git clone --recursive --depth=1 https://github.com/openhwgroup/cva6 cva6
stage - (1.3 sec in block)Simulation
stage block (Simulation) - (0.92 sec in block)
dir - (0.54 sec in block)cva6
dir block - (0.31 sec in block)
echo - (0.11 sec in self)simulation not supported for System Verilog files
stage - (2 sec in block)Utilities
stage block (Utilities) - (1.5 sec in block)
dir - (1 sec in block)cva6
dir block - (0.72 sec in block)
sh - (0.49 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (6.9 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (6.3 sec in block)
getContext - (0.27 sec in self)
parallel - (5.7 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (5.3 sec in block)
stage - (4.9 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (4.4 sec in block)
getContext - (0.38 sec in self)
stage - (0.98 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.39 sec in block)
getContext - (0.17 sec in self)
stage - (0.94 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (0.66 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.8 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.56 sec in block)
junit - (0.29 sec in self)**/*.xml