Start of Pipeline - (55 sec in block) | | | |
|
node - (54 sec in block) | | | |
|
node block - (54 sec in block) | | | |
|
stage - (3.5 sec in block) | Git Clone | | |
|
stage block (Git Clone) - (3 sec in block) | | | |
|
sh - (0.49 sec in self) | rm -rf *.xml | | |
|
sh - (0.68 sec in self) | rm -rf cv32e40x | | |
|
sh - (1.6 sec in self) | git clone --recursive --depth=1 https://github.com/openhwgroup/cv32e40x cv32e40x | | |
|
stage - (1.4 sec in block) | Simulation | | |
|
stage block (Simulation) - (0.96 sec in block) | | | |
|
dir - (0.55 sec in block) | cv32e40x | | |
|
dir block - (0.32 sec in block) | | | |
|
echo - (0.11 sec in self) | simulation not supported for System Verilog files | | |
|
stage - (1.7 sec in block) | Utilities | | |
|
stage block (Utilities) - (1.3 sec in block) | | | |
|
dir - (0.9 sec in block) | cv32e40x | | |
|
dir block - (0.64 sec in block) | | | |
|
sh - (0.41 sec in self) | python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels | | |
|
stage - (46 sec in block) | FPGA Build Pipeline | | |
|
stage block (FPGA Build Pipeline) - (45 sec in block) | | | |
|
parallel - (45 sec in block) | | | |
|
parallel block (Branch: digilent_arty_a7_100t) - (44 sec in block) | | | |
|
stage - (44 sec in block) | digilent_arty_a7_100t | | |
|
stage block (digilent_arty_a7_100t) - (44 sec in block) | | | |
|
lock - (43 sec in block) | digilent_arty_a7_100t | | |
|
lock block - (42 sec in block) | | | |
|
stage - (40 sec in block) | Synthesis and PnR | | |
|
stage block (Synthesis and PnR) - (40 sec in block) | | | |
|
dir - (39 sec in block) | cv32e40x | | |
|
dir block - (39 sec in block) | | | |
|
echo - (0.17 sec in self) | Starting synthesis for FPGA digilent_arty_a7_100t. | | |
|
sh - (39 sec in self) | python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p cv32e40x -b digilent_arty_a7_100t | | |
|
stage - (0.99 sec in block) | Flash digilent_arty_a7_100t | | |
|
stage block (Flash digilent_arty_a7_100t) - (0.38 sec in block) | | | |
|
getContext - (0.17 sec in self) | | | |
|
stage - (0.69 sec in block) | Test digilent_arty_a7_100t | | |
|
stage block (Test digilent_arty_a7_100t) - (0.39 sec in block) | | | |
|
getContext - (0.17 sec in self) | | | |
|
stage - (0.77 sec in block) | Declarative: Post Actions | | |
|
stage block (Declarative: Post Actions) - (0.53 sec in block) | | | |
|
junit - (0.28 sec in self) | **/*.xml | | |
|