Console Output

+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p cv32e40p -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/cv32e40p/cv32e40p/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-36] 'cv32e40p_pkg' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:29]
ERROR: [Synth 8-36] 'alu_opcode_e' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:34]
ERROR: [Synth 8-36] 'ALU_SUB' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:102]
ERROR: [Synth 8-36] 'ALU_SUBR' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:102]
ERROR: [Synth 8-36] 'ALU_SUBU' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:103]
ERROR: [Synth 8-36] 'ALU_SUBUR' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:103]
ERROR: [Synth 8-36] 'ALU_ABS' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:106]
ERROR: [Synth 8-36] 'ALU_ABS' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:135]
ERROR: [Synth 8-36] 'ALU_CLIP' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:135]
ERROR: [Synth 8-36] 'VEC_MODE16' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:140]
ERROR: [Synth 8-36] 'VEC_MODE8' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:144]
ERROR: [Synth 8-36] 'VEC_MODE16' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:154]
ERROR: [Synth 8-36] 'VEC_MODE8' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:158]
ERROR: [Synth 8-36] 'ALU_ADDR' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:181]
ERROR: [Synth 8-36] 'ALU_SUBR' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:181]
ERROR: [Synth 8-36] 'ALU_ADDUR' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:182]
ERROR: [Synth 8-36] 'ALU_SUBUR' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:182]
ERROR: [Synth 8-36] 'VEC_MODE16' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:218]
ERROR: [Synth 8-36] 'VEC_MODE8' is not declared [/var/jenkins_home/workspace/cv32e40p/cv32e40p/rtl/cv32e40p_alu.sv:223]
ERROR: [Synth 8-439] module 'Controller' not found [/eda/processor_ci/rtl/cv32e40p.sv:69]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/cv32e40p.sv:5]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 296, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.