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Start of Pipeline - (19 sec in block)
node - (18 sec in block)
node block - (17 sec in block)
stage - (3.4 sec in block)Git Clone
stage block (Git Clone) - (2.9 sec in block)
sh - (0.46 sec in self)rm -rf cv32e40p
sh - (2.2 sec in self)git clone --recursive https://github.com/openhwgroup/cv32e40p cv32e40p
stage - (2.1 sec in block)Simulation
stage block (Simulation) - (1.5 sec in block)
dir - (1 sec in block)cv32e40p
dir block - (0.7 sec in block)
sh - (0.48 sec in self)iverilog -o simulation.out -g2005-sv -s -I rtl/include/ rtl/cv32e40p_aligner.sv rtl/cv32e40p_alu.sv rtl/cv32e40p_alu_div.sv rtl/cv32e40p_apu_disp.sv rtl/cv32e40p_compressed_decoder.sv rtl/cv32e40p_controller.sv rtl/cv32e40p_core.sv rtl/cv32e40p_cs_registers.sv rtl/cv32e40p_decoder.sv rtl/cv32e40p_ex_stage.sv rtl/cv32e40p_ff_one.sv rtl/cv32e40p_fifo.sv rtl/cv32e40p_fp_wrapper.sv rtl/cv32e40p_hwloop_regs.sv rtl/cv32e40p_id_stage.sv rtl/cv32e40p_if_stage.sv rtl/cv32e40p_int_controller.sv rtl/cv32e40p_load_store_unit.sv rtl/cv32e40p_mult.sv rtl/cv32e40p_obi_interface.sv rtl/cv32e40p_popcnt.sv rtl/cv32e40p_prefetch_buffer.sv rtl/cv32e40p_prefetch_controller.sv rtl/cv32e40p_register_file_ff.sv rtl/cv32e40p_register_file_latch.sv rtl/cv32e40p_sleep_unit.sv rtl/cv32e40p_top.sv
stage - (10 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (9.7 sec in block)
getContext - (0.32 sec in self)
parallel - (9 sec in block)
parallel block (Branch: colorlight_i9) - (84 ms in block)
stage - (7.4 sec in block)colorlight_i9
stage block (colorlight_i9) - (7 sec in block)
getContext - (0.88 sec in self)
stage - (1.8 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (0.68 sec in block)
getContext - (0.18 sec in self)
stage - (1.9 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.64 sec in block)
getContext - (0.2 sec in self)
stage - (1.4 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.68 sec in block)
getContext - (0.19 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (8.2 sec in block)
stage - (7.3 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (6.8 sec in block)
getContext - (0.81 sec in self)
stage - (1.8 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (0.75 sec in block)
getContext - (0.16 sec in self)
stage - (1.9 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.82 sec in block)
getContext - (0.2 sec in self)
stage - (1.4 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.84 sec in block)
getContext - (0.2 sec in self)
stage - (1.6 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.4 sec in block)
dir - (0.91 sec in block)cv32e40p
dir block - (0.65 sec in block)
sh - (0.43 sec in self)rm -rf *