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Start of Pipeline - (59 min in block)
node - (59 min in block)
node block - (59 min in block)
stage - (2.4 sec in block)Git Clone
stage block (Git Clone) - (1.9 sec in block)
sh - (0.47 sec in self)rm -rf biriscv
sh - (1.2 sec in self)git clone --recursive https://github.com/ultraembedded/biriscv biriscv
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.85 sec in block)biriscv
dir block - (0.61 sec in block)
sh - (0.4 sec in self)iverilog -o simulation.out -g2005 -s riscv_core -I src/core src/core/biriscv_alu.v src/core/biriscv_csr.v src/core/biriscv_csr_regfile.v src/core/biriscv_decode.v src/core/biriscv_decoder.v src/core/biriscv_defs.v src/core/biriscv_divider.v src/core/biriscv_exec.v src/core/biriscv_fetch.v src/core/biriscv_frontend.v src/core/biriscv_issue.v src/core/biriscv_lsu.v src/core/biriscv_mmu.v src/core/biriscv_multiplier.v src/core/biriscv_npc.v src/core/biriscv_pipe_ctrl.v src/core/biriscv_regfile.v src/core/biriscv_trace_sim.v src/core/biriscv_xilinx_2r1w.v src/core/riscv_core.v
stage - (58 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (58 min in block)
parallel - (58 min in block)
parallel block (Branch: colorlight_i9) - (67 ms in block)
stage - (35 min in block)colorlight_i9
stage block (colorlight_i9) - (35 min in block)
lock - (35 min in block)colorlight_i9
lock block - (35 min in block)
stage - (34 min in block)Síntese e PnR
stage block (Síntese e PnR) - (34 min in block)
dir - (34 min in block)biriscv
dir block - (34 min in block)
echo - (0.16 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (34 min in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p biriscv -b colorlight_i9
stage - (28 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (27 sec in block)
dir - (27 sec in block)biriscv
dir block - (27 sec in block)
echo - (0.2 sec in self)FPGA colorlight_i9 bloqueada para flash.
sh - (26 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p biriscv -b colorlight_i9 -l
stage - (6.3 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (6 sec in block)
echo - (0.22 sec in self)Testando FPGA colorlight_i9.
dir - (5.5 sec in block)biriscv
dir block - (5.2 sec in block)
sh - (5 sec in self)PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py
parallel block (Branch: digilent_nexys4_ddr) - (58 min in block)
stage - (58 min in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (58 min in block)
lock - (58 min in block)digilent_nexys4_ddr
lock block - (43 min in block)
stage - (43 min in block)Síntese e PnR
stage block (Síntese e PnR) - (43 min in block)
dir - (43 min in block)biriscv
dir block - (43 min in block)
echo - (0.34 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (43 min in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p biriscv -b digilent_nexys4_ddr
stage - (14 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (13 sec in block)
dir - (13 sec in block)biriscv
dir block - (12 sec in block)
echo - (0.2 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
sh - (12 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p biriscv -b digilent_nexys4_ddr -l
stage - (1.1 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.95 sec in block)
echo - (0.22 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.4 sec in block)biriscv
dir block - (0.14 sec in block)
stage - (1 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.78 sec in block)
junit - (0.53 sec in self)**/test-reports/*.xml