Console Output
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p biriscv -b digilent_nexys4_ddr
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/biriscv/biriscv/build_digilent_nexys4_ddr.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
Building the Design...
/eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/lib/jenkins/workspace/biriscv/biriscv/build_digilent_nexys4_ddr.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096"
****** Vivado v2023.2 (64-bit)
**** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source /var/lib/jenkins/workspace/biriscv/biriscv/build_digilent_nexys4_ddr.tcl
# read_verilog /eda/processor-ci/rtl/biriscv.v
read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1305.215 ; gain = 0.023 ; free physical = 2797 ; free virtual = 25920
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_alu.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_csr.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_csr_regfile.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_decode.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_decoder.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_defs.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_divider.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_exec.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_fetch.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_frontend.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_issue.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_lsu.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_mmu.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_multiplier.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_npc.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_pipe_ctrl.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_regfile.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_trace_sim.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_xilinx_2r1w.v
# read_verilog /var/lib/jenkins/workspace/biriscv/biriscv/src/core/riscv_core.v
# set ID 0x6a6a6a6a
# set CLOCK_FREQ 50000000
# read_verilog /eda/processor-ci-controller/modules/uart.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
# read_verilog /eda/processor-ci-controller/src/fifo.v
# read_verilog /eda/processor-ci-controller/src/reset.v
# read_verilog /eda/processor-ci-controller/src/clk_divider.v
# read_verilog /eda/processor-ci-controller/src/memory.v
# read_verilog /eda/processor-ci-controller/src/interpreter.v
# read_verilog /eda/processor-ci-controller/src/controller.v
# set ID [lindex $argv 0]
# set CLOCK_FREQ [lindex $argv 1]
# set MEMORY_SIZE [lindex $argv 2]
# read_xdc "/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc"
# set_property PROCESSING_ORDER EARLY [get_files /eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
# synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE
Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 3398999
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2028.938 ; gain = 403.715 ; free physical = 1820 ; free virtual = 24944
---------------------------------------------------------------------------------
CRITICAL WARNING: [Synth 8-9339] data object 'reset_o' is already declared [/eda/processor-ci/rtl/biriscv.v:173]
INFO: [Synth 8-6826] previous declaration of 'reset_o' is from here [/eda/processor-ci/rtl/biriscv.v:29]
CRITICAL WARNING: [Synth 8-11152] second declaration of 'reset_o' is ignored [/eda/processor-ci/rtl/biriscv.v:173]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16]
WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15]
WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16]
WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17]
WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84]
WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85]
INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor-ci/rtl/biriscv.v:1]
INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
Parameter ID bound to: 0 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 4096 - type: integer
INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1]
Parameter COUNTER_BITS bound to: 32 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1]
INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter ID bound to: 0 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213]
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1]
Parameter DEPTH bound to: 8 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1]
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 4096 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1]
WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268]
INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1]
INFO: [Synth 8-6157] synthesizing module 'riscv_core' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/riscv_core.v:26]
INFO: [Synth 8-6157] synthesizing module 'biriscv_frontend' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_frontend.v:26]
Parameter SUPPORT_BRANCH_PREDICTION bound to: 1 - type: integer
Parameter SUPPORT_MULDIV bound to: 1 - type: integer
Parameter SUPPORT_MMU bound to: 0 - type: integer
Parameter EXTRA_DECODE_STAGE bound to: 0 - type: integer
Parameter NUM_BTB_ENTRIES bound to: 32 - type: integer
Parameter NUM_BTB_ENTRIES_W bound to: 5 - type: integer
Parameter NUM_BHT_ENTRIES bound to: 512 - type: integer
Parameter NUM_BHT_ENTRIES_W bound to: 9 - type: integer
Parameter RAS_ENABLE bound to: 1 - type: integer
Parameter GSHARE_ENABLE bound to: 0 - type: integer
Parameter BHT_ENABLE bound to: 1 - type: integer
Parameter NUM_RAS_ENTRIES bound to: 8 - type: integer
Parameter NUM_RAS_ENTRIES_W bound to: 3 - type: integer
INFO: [Synth 8-6157] synthesizing module 'biriscv_npc' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_npc.v:26]
Parameter SUPPORT_BRANCH_PREDICTION bound to: 1 - type: integer
Parameter NUM_BTB_ENTRIES bound to: 32 - type: integer
Parameter NUM_BTB_ENTRIES_W bound to: 5 - type: integer
Parameter NUM_BHT_ENTRIES bound to: 512 - type: integer
Parameter NUM_BHT_ENTRIES_W bound to: 9 - type: integer
Parameter RAS_ENABLE bound to: 1 - type: integer
Parameter GSHARE_ENABLE bound to: 0 - type: integer
Parameter BHT_ENABLE bound to: 1 - type: integer
Parameter NUM_RAS_ENTRIES bound to: 8 - type: integer
Parameter NUM_RAS_ENTRIES_W bound to: 3 - type: integer
INFO: [Synth 8-6157] synthesizing module 'biriscv_npc_lfsr' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_npc.v:399]
Parameter DEPTH bound to: 32 - type: integer
Parameter ADDR_W bound to: 5 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'biriscv_npc_lfsr' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_npc.v:399]
INFO: [Synth 8-6155] done synthesizing module 'biriscv_npc' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_npc.v:26]
INFO: [Synth 8-6157] synthesizing module 'biriscv_decode' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_decode.v:26]
Parameter SUPPORT_MULDIV bound to: 1 - type: integer
Parameter EXTRA_DECODE_STAGE bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'fetch_fifo' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_decode.v:279]
Parameter OPC_INFO_W bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'fetch_fifo' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_decode.v:279]
INFO: [Synth 8-6157] synthesizing module 'biriscv_decoder' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_decoder.v:27]
INFO: [Synth 8-6155] done synthesizing module 'biriscv_decoder' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_decoder.v:27]
INFO: [Synth 8-6155] done synthesizing module 'biriscv_decode' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_decode.v:26]
INFO: [Synth 8-6157] synthesizing module 'biriscv_fetch' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_fetch.v:26]
Parameter SUPPORT_MMU bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'biriscv_fetch' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_fetch.v:26]
INFO: [Synth 8-6155] done synthesizing module 'biriscv_frontend' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_frontend.v:26]
INFO: [Synth 8-6157] synthesizing module 'biriscv_mmu' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_mmu.v:26]
Parameter MEM_CACHE_ADDR_MIN bound to: -2147483648 - type: integer
Parameter MEM_CACHE_ADDR_MAX bound to: -1879048193 - type: integer
Parameter SUPPORT_MMU bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'biriscv_mmu' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_mmu.v:26]
INFO: [Synth 8-6157] synthesizing module 'biriscv_lsu' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_lsu.v:26]
Parameter MEM_CACHE_ADDR_MIN bound to: -2147483648 - type: integer
Parameter MEM_CACHE_ADDR_MAX bound to: -1879048193 - type: integer
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_lsu.v:208]
INFO: [Synth 8-6157] synthesizing module 'biriscv_lsu_fifo' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_lsu.v:422]
Parameter WIDTH bound to: 36 - type: integer
Parameter DEPTH bound to: 2 - type: integer
Parameter ADDR_W bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'biriscv_lsu_fifo' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_lsu.v:422]
INFO: [Synth 8-6155] done synthesizing module 'biriscv_lsu' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_lsu.v:26]
INFO: [Synth 8-6157] synthesizing module 'biriscv_csr' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_csr.v:26]
Parameter SUPPORT_MULDIV bound to: 1 - type: integer
Parameter SUPPORT_SUPER bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'biriscv_csr_regfile' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_csr_regfile.v:25]
Parameter SUPPORT_MTIMECMP bound to: 1 - type: integer
Parameter SUPPORT_SUPER bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'biriscv_csr_regfile' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_csr_regfile.v:25]
INFO: [Synth 8-6155] done synthesizing module 'biriscv_csr' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_csr.v:26]
INFO: [Synth 8-6157] synthesizing module 'biriscv_multiplier' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_multiplier.v:26]
INFO: [Synth 8-6155] done synthesizing module 'biriscv_multiplier' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_multiplier.v:26]
INFO: [Synth 8-6157] synthesizing module 'biriscv_divider' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_divider.v:26]
INFO: [Synth 8-6155] done synthesizing module 'biriscv_divider' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_divider.v:26]
INFO: [Synth 8-6157] synthesizing module 'biriscv_issue' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_issue.v:26]
Parameter SUPPORT_MULDIV bound to: 1 - type: integer
Parameter SUPPORT_DUAL_ISSUE bound to: 1 - type: integer
Parameter SUPPORT_LOAD_BYPASS bound to: 1 - type: integer
Parameter SUPPORT_MUL_BYPASS bound to: 1 - type: integer
Parameter SUPPORT_REGFILE_XILINX bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'biriscv_pipe_ctrl' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_pipe_ctrl.v:25]
Parameter SUPPORT_LOAD_BYPASS bound to: 1 - type: integer
Parameter SUPPORT_MUL_BYPASS bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'biriscv_pipe_ctrl' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_pipe_ctrl.v:25]
INFO: [Synth 8-6157] synthesizing module 'biriscv_regfile' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_regfile.v:25]
Parameter SUPPORT_REGFILE_XILINX bound to: 0 - type: integer
Parameter SUPPORT_DUAL_ISSUE bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'biriscv_regfile' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_regfile.v:25]
INFO: [Synth 8-6155] done synthesizing module 'biriscv_issue' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_issue.v:26]
INFO: [Synth 8-6157] synthesizing module 'biriscv_exec' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_exec.v:26]
INFO: [Synth 8-6157] synthesizing module 'biriscv_alu' [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_alu.v:25]
INFO: [Synth 8-6155] done synthesizing module 'biriscv_alu' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_alu.v:25]
INFO: [Synth 8-6155] done synthesizing module 'biriscv_exec' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_exec.v:26]
INFO: [Synth 8-6155] done synthesizing module 'riscv_core' (0#1) [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/riscv_core.v:26]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1]
Parameter CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1]
WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor-ci/rtl/biriscv.v:177]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor-ci/rtl/biriscv.v:177]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor-ci/rtl/biriscv.v:177]
INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor-ci/rtl/biriscv.v:1]
WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25]
WARNING: [Synth 8-6014] Unused sequential element BRANCH_PREDICTION.global_history_real_q_reg was removed. [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_npc.v:173]
WARNING: [Synth 8-6014] Unused sequential element BRANCH_PREDICTION.global_history_q_reg was removed. [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_npc.v:184]
WARNING: [Synth 8-6014] Unused sequential element csr_medeleg_q_reg was removed. [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_csr_regfile.v:498]
WARNING: [Synth 8-6014] Unused sequential element csr_scause_q_reg was removed. [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_csr_regfile.v:504]
WARNING: [Synth 8-6014] Unused sequential element csr_stval_q_reg was removed. [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_csr_regfile.v:505]
WARNING: [Synth 8-6014] Unused sequential element csr_sscratch_q_reg was removed. [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_csr_regfile.v:507]
WARNING: [Synth 8-6014] Unused sequential element result_e3_q_reg was removed. [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_multiplier.v:138]
WARNING: [Synth 8-6014] Unused sequential element npc_e1_q_reg was removed. [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_pipe_ctrl.v:156]
WARNING: [Synth 8-6014] Unused sequential element npc_e2_q_reg was removed. [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_pipe_ctrl.v:236]
WARNING: [Synth 8-6014] Unused sequential element npc_wb_q_reg was removed. [/var/lib/jenkins/workspace/biriscv/biriscv/src/core/biriscv_pipe_ctrl.v:362]
WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/biriscv.v:21]
WARNING: [Synth 8-3848] Net memory_write in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/biriscv.v:30]
WARNING: [Synth 8-7129] Port opcode_invalid_i in module biriscv_exec is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rb_idx_i[4] in module biriscv_exec is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rb_idx_i[3] in module biriscv_exec is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rb_idx_i[2] in module biriscv_exec is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rb_idx_i[1] in module biriscv_exec is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rb_idx_i[0] in module biriscv_exec is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_rd_i[4] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_rd_i[3] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_rd_i[2] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_rd_i[1] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_rd_i[0] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[31] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[30] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[29] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[28] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[27] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[26] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[25] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[24] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[23] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[22] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[21] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[20] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[19] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[18] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[17] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[16] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[15] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[14] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[13] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[12] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[11] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[10] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[9] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[8] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[7] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[6] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[5] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[4] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[3] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port issue_branch_target_i[2] in module biriscv_pipe_ctrl is either unconnected or has no load
WARNING: [Synth 8-7129] Port branch_exec0_request_i in module biriscv_issue is either unconnected or has no load
WARNING: [Synth 8-7129] Port branch_d_exec0_priv_i[1] in module biriscv_issue is either unconnected or has no load
WARNING: [Synth 8-7129] Port branch_d_exec0_priv_i[0] in module biriscv_issue is either unconnected or has no load
WARNING: [Synth 8-7129] Port branch_d_exec1_priv_i[1] in module biriscv_issue is either unconnected or has no load
WARNING: [Synth 8-7129] Port branch_d_exec1_priv_i[0] in module biriscv_issue is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[31] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[30] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[29] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[28] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[27] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[26] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[25] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[24] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[23] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[22] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[21] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[20] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[19] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[18] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[17] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[16] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[15] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[14] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[13] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[12] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[11] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[10] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[9] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[8] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[7] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[6] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[5] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[4] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[3] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[2] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[1] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[0] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_invalid_i in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rd_idx_i[4] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rd_idx_i[3] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rd_idx_i[2] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rd_idx_i[1] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rd_idx_i[0] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_ra_idx_i[4] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_ra_idx_i[3] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_ra_idx_i[2] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_ra_idx_i[1] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_ra_idx_i[0] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rb_idx_i[4] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rb_idx_i[3] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rb_idx_i[2] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rb_idx_i[1] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_rb_idx_i[0] in module biriscv_divider is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[31] in module biriscv_multiplier is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[30] in module biriscv_multiplier is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[29] in module biriscv_multiplier is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[28] in module biriscv_multiplier is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[27] in module biriscv_multiplier is either unconnected or has no load
WARNING: [Synth 8-7129] Port opcode_pc_i[26] in module biriscv_multiplier is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2240.477 ; gain = 615.254 ; free physical = 1594 ; free virtual = 24721
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2255.320 ; gain = 630.098 ; free physical = 1599 ; free virtual = 24726
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2255.320 ; gain = 630.098 ; free physical = 1599 ; free virtual = 24726
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2255.320 ; gain = 0.000 ; free physical = 1590 ; free virtual = 24717
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2405.070 ; gain = 0.000 ; free physical = 1566 ; free virtual = 24693
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2405.105 ; gain = 0.000 ; free physical = 1569 ; free virtual = 24696
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:54 ; elapsed = 00:00:54 . Memory (MB): peak = 2405.105 ; gain = 779.883 ; free physical = 1556 ; free virtual = 24683
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:54 ; elapsed = 00:00:54 . Memory (MB): peak = 2405.105 ; gain = 779.883 ; free physical = 1555 ; free virtual = 24682
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:54 ; elapsed = 00:00:54 . Memory (MB): peak = 2405.105 ; gain = 779.883 ; free physical = 1555 ; free virtual = 24682
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
READ | 001 | 0001
COPY_READ_BUFFER | 010 | 0100
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
COPY_WRITE_BUFFER | 001 | 0100
WRITE | 010 | 0001
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE | 0001 | 00
iSTATE0 | 0010 | 01
iSTATE1 | 0100 | 10
iSTATE2 | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:17 ; elapsed = 00:01:17 . Memory (MB): peak = 2405.105 ; gain = 779.883 ; free physical = 1562 ; free virtual = 24692
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 3
2 Input 32 Bit Adders := 26
3 Input 32 Bit Adders := 6
2 Input 24 Bit Adders := 2
2 Input 10 Bit Adders := 2
2 Input 8 Bit Adders := 1
2 Input 6 Bit Adders := 4
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 6
2 Input 2 Bit Adders := 5
2 Input 1 Bit Adders := 4
+---XORs :
2 Input 32 Bit XORs := 2
2 Input 16 Bit XORs := 1
+---Registers :
100 Bit Registers := 1
64 Bit Registers := 4
63 Bit Registers := 1
36 Bit Registers := 2
33 Bit Registers := 2
32 Bit Registers := 183
24 Bit Registers := 5
16 Bit Registers := 1
10 Bit Registers := 8
8 Bit Registers := 11
6 Bit Registers := 8
4 Bit Registers := 3
3 Bit Registers := 4
2 Bit Registers := 522
1 Bit Registers := 191
+---RAMs :
32K Bit (1024 X 32 bit) RAMs := 2
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
2 Input 100 Bit Muxes := 1
2 Input 64 Bit Muxes := 4
4 Input 64 Bit Muxes := 1
48 Input 64 Bit Muxes := 2
2 Input 63 Bit Muxes := 2
2 Input 36 Bit Muxes := 1
3 Input 33 Bit Muxes := 2
2 Input 33 Bit Muxes := 4
2 Input 32 Bit Muxes := 212
4 Input 32 Bit Muxes := 6
3 Input 32 Bit Muxes := 6
23 Input 32 Bit Muxes := 1
14 Input 32 Bit Muxes := 1
11 Input 32 Bit Muxes := 4
7 Input 32 Bit Muxes := 2
5 Input 32 Bit Muxes := 1
48 Input 24 Bit Muxes := 1
2 Input 16 Bit Muxes := 3
2 Input 13 Bit Muxes := 2
2 Input 12 Bit Muxes := 1
2 Input 10 Bit Muxes := 8
4 Input 8 Bit Muxes := 2
48 Input 8 Bit Muxes := 2
2 Input 8 Bit Muxes := 4
24 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 2
2 Input 6 Bit Muxes := 21
5 Input 6 Bit Muxes := 1
3 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 11
3 Input 5 Bit Muxes := 2
7 Input 5 Bit Muxes := 1
9 Input 4 Bit Muxes := 1
25 Input 4 Bit Muxes := 1
7 Input 4 Bit Muxes := 2
11 Input 4 Bit Muxes := 4
2 Input 4 Bit Muxes := 6
3 Input 3 Bit Muxes := 2
2 Input 3 Bit Muxes := 20
4 Input 3 Bit Muxes := 2
5 Input 3 Bit Muxes := 4
2 Input 2 Bit Muxes := 32
21 Input 2 Bit Muxes := 1
3 Input 2 Bit Muxes := 3
4 Input 2 Bit Muxes := 6
48 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1371
3 Input 1 Bit Muxes := 36
5 Input 1 Bit Muxes := 12
22 Input 1 Bit Muxes := 3
4 Input 1 Bit Muxes := 4
8 Input 1 Bit Muxes := 4
32 Input 1 Bit Muxes := 4
33 Input 1 Bit Muxes := 1
48 Input 1 Bit Muxes := 22
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
DSP Report: Generating DSP u_mul/mult_result_w, operation Mode is: A*B.
DSP Report: operator u_mul/mult_result_w is absorbed into DSP u_mul/mult_result_w.
DSP Report: operator u_mul/mult_result_w is absorbed into DSP u_mul/mult_result_w.
DSP Report: Generating DSP u_mul/mult_result_w, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator u_mul/mult_result_w is absorbed into DSP u_mul/mult_result_w.
DSP Report: operator u_mul/mult_result_w is absorbed into DSP u_mul/mult_result_w.
DSP Report: Generating DSP u_mul/mult_result_w, operation Mode is: A*B.
DSP Report: operator u_mul/mult_result_w is absorbed into DSP u_mul/mult_result_w.
DSP Report: operator u_mul/mult_result_w is absorbed into DSP u_mul/mult_result_w.
DSP Report: Generating DSP u_mul/mult_result_w, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator u_mul/mult_result_w is absorbed into DSP u_mul/mult_result_w.
DSP Report: operator u_mul/mult_result_w is absorbed into DSP u_mul/mult_result_w.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:15:08 ; elapsed = 00:15:16 . Memory (MB): peak = 2626.633 ; gain = 1001.410 ; free physical = 1122 ; free virtual = 24282
---------------------------------------------------------------------------------
Sort Area is riscv_core__GB0 u_mul/mult_result_w_3 : 0 0 : 2701 5008 : Used 1 time 0
Sort Area is riscv_core__GB0 u_mul/mult_result_w_3 : 0 1 : 2307 5008 : Used 1 time 0
Sort Area is riscv_core__GB0 u_mul/mult_result_w_0 : 0 0 : 2304 4330 : Used 1 time 0
Sort Area is riscv_core__GB0 u_mul/mult_result_w_0 : 0 1 : 2026 4330 : Used 1 time 0
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1 | LUT |
|Interpreter | memory_mux_selector | 256x1 | LUT |
+------------+---------------------+---------------+----------------+
Distributed RAM: Preliminary Mapping Report (see note below)
+----------------+------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------+------------------------------------+-----------+----------------------+------------------+
|processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
|processorci_top | Controller/Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+----------------+------------------------------------+-----------+----------------------+------------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+-------------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+-------------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|biriscv_multiplier | A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|biriscv_multiplier | (PCIN>>17)+A*B | 16 | 16 | - | - | 30 | 0 | 0 | - | - | - | 0 | 0 |
|biriscv_multiplier | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|biriscv_multiplier | (PCIN>>17)+A*B | 18 | 16 | - | - | 47 | 0 | 0 | - | - | - | 0 | 0 |
+-------------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:15:24 ; elapsed = 00:15:32 . Memory (MB): peak = 2626.633 ; gain = 1001.410 ; free physical = 1120 ; free virtual = 24279
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:18:50 ; elapsed = 00:18:58 . Memory (MB): peak = 2626.633 ; gain = 1001.410 ; free physical = 1105 ; free virtual = 24265
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+----------------+------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------+------------------------------------+-----------+----------------------+------------------+
|processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
|processorci_top | Controller/Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+----------------+------------------------------------+-----------+----------------------+------------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:19:14 ; elapsed = 00:19:23 . Memory (MB): peak = 2748.633 ; gain = 1123.410 ; free physical = 1800 ; free virtual = 25073
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:19:26 ; elapsed = 00:19:34 . Memory (MB): peak = 2748.633 ; gain = 1123.410 ; free physical = 1811 ; free virtual = 25083
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:19:26 ; elapsed = 00:19:34 . Memory (MB): peak = 2748.633 ; gain = 1123.410 ; free physical = 1809 ; free virtual = 25081
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:19:33 ; elapsed = 00:19:42 . Memory (MB): peak = 2748.633 ; gain = 1123.410 ; free physical = 1799 ; free virtual = 25071
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:19:34 ; elapsed = 00:19:42 . Memory (MB): peak = 2748.633 ; gain = 1123.410 ; free physical = 1805 ; free virtual = 25077
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:19:35 ; elapsed = 00:19:43 . Memory (MB): peak = 2748.633 ; gain = 1123.410 ; free physical = 1811 ; free virtual = 25083
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:19:35 ; elapsed = 00:19:43 . Memory (MB): peak = 2748.633 ; gain = 1123.410 ; free physical = 1811 ; free virtual = 25083
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
DSP Final Report (the ' indicates corresponding REG is set)
+-------------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+-------------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|biriscv_multiplier | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|biriscv_multiplier | PCIN>>17+A*B | 30 | 18 | - | - | 30 | 0 | 0 | - | - | - | 0 | 0 |
|biriscv_multiplier | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|biriscv_multiplier | PCIN>>17+A*B | 0 | 18 | - | - | 47 | 0 | 0 | - | - | - | 0 | 0 |
+-------------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 583|
|3 |DSP48E1 | 4|
|4 |LUT1 | 169|
|5 |LUT2 | 958|
|6 |LUT3 | 1126|
|7 |LUT4 | 1074|
|8 |LUT5 | 1312|
|9 |LUT6 | 5320|
|10 |MUXF7 | 539|
|11 |MUXF8 | 235|
|12 |RAM256X1S | 256|
|13 |RAM32M | 2|
|14 |RAM32X1D | 4|
|15 |FDCE | 3985|
|16 |FDPE | 1034|
|17 |FDRE | 1656|
|18 |FDSE | 5|
|19 |IBUF | 2|
|20 |OBUF | 2|
|21 |OBUFT | 1|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:19:35 ; elapsed = 00:19:43 . Memory (MB): peak = 2748.633 ; gain = 1123.410 ; free physical = 1811 ; free virtual = 25083
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:19:24 ; elapsed = 00:19:33 . Memory (MB): peak = 2748.633 ; gain = 973.625 ; free physical = 1814 ; free virtual = 25087
Synthesis Optimization Complete : Time (s): cpu = 00:19:35 ; elapsed = 00:19:44 . Memory (MB): peak = 2748.641 ; gain = 1123.410 ; free physical = 1814 ; free virtual = 25087
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2748.641 ; gain = 0.000 ; free physical = 2092 ; free virtual = 25364
INFO: [Netlist 29-17] Analyzing 1623 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2844.680 ; gain = 0.000 ; free physical = 2097 ; free virtual = 25370
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 262 instances were transformed.
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 560385da
INFO: [Common 17-83] Releasing license: Synthesis
91 Infos, 128 Warnings, 2 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:19:59 ; elapsed = 00:20:03 . Memory (MB): peak = 2844.715 ; gain = 1539.500 ; free physical = 2104 ; free virtual = 25377
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2585.906; main = 2294.112; forked = 434.844
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3758.305; main = 2844.684; forked = 1009.668
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2908.711 ; gain = 63.996 ; free physical = 2104 ; free virtual = 25377
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: ab2b9a9e
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2908.711 ; gain = 0.000 ; free physical = 2097 ; free virtual = 25371
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: ab2b9a9e
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2908.711 ; gain = 0.000 ; free physical = 2065 ; free virtual = 25339
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: ab2b9a9e
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2908.711 ; gain = 0.000 ; free physical = 2065 ; free virtual = 25339
Phase 1 Initialization | Checksum: ab2b9a9e
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2908.711 ; gain = 0.000 ; free physical = 2065 ; free virtual = 25339
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: ab2b9a9e
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2908.711 ; gain = 0.000 ; free physical = 2060 ; free virtual = 25333
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: ab2b9a9e
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2908.711 ; gain = 0.000 ; free physical = 2062 ; free virtual = 25336
Phase 2 Timer Update And Timing Data Collection | Checksum: ab2b9a9e
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2908.711 ; gain = 0.000 ; free physical = 2062 ; free virtual = 25336
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 8 inverters resulting in an inversion of 367 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 15059c492
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2908.711 ; gain = 0.000 ; free physical = 2053 ; free virtual = 25327
Retarget | Checksum: 15059c492
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 11 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 12f746f8e
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2908.711 ; gain = 0.000 ; free physical = 2032 ; free virtual = 25305
Constant propagation | Checksum: 12f746f8e
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 18715f5cc
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2908.711 ; gain = 0.000 ; free physical = 2005 ; free virtual = 25279
Sweep | Checksum: 18715f5cc
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 18715f5cc
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2940.727 ; gain = 32.016 ; free physical = 1998 ; free virtual = 25272
BUFG optimization | Checksum: 18715f5cc
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 18715f5cc
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2940.727 ; gain = 32.016 ; free physical = 1998 ; free virtual = 25272
Shift Register Optimization | Checksum: 18715f5cc
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 18715f5cc
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2940.727 ; gain = 32.016 ; free physical = 1998 ; free virtual = 25272
Post Processing Netlist | Checksum: 18715f5cc
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1cdb13944
Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2940.727 ; gain = 32.016 ; free physical = 1992 ; free virtual = 25265
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2940.727 ; gain = 0.000 ; free physical = 1992 ; free virtual = 25265
Phase 9.2 Verifying Netlist Connectivity | Checksum: 1cdb13944
Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2940.727 ; gain = 32.016 ; free physical = 1992 ; free virtual = 25265
Phase 9 Finalization | Checksum: 1cdb13944
Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2940.727 ; gain = 32.016 ; free physical = 1992 ; free virtual = 25265
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 11 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 1cdb13944
Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2940.727 ; gain = 32.016 ; free physical = 1992 ; free virtual = 25265
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2940.727 ; gain = 0.000 ; free physical = 1989 ; free virtual = 25263
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1cdb13944
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2940.727 ; gain = 0.000 ; free physical = 1991 ; free virtual = 25264
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1cdb13944
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2940.727 ; gain = 0.000 ; free physical = 1990 ; free virtual = 25264
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2940.727 ; gain = 0.000 ; free physical = 1990 ; free virtual = 25263
Ending Netlist Obfuscation Task | Checksum: 1cdb13944
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2940.727 ; gain = 0.000 ; free physical = 1989 ; free virtual = 25263
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 2940.727 ; gain = 96.012 ; free physical = 1988 ; free virtual = 25262
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2972.742 ; gain = 0.000 ; free physical = 1993 ; free virtual = 25266
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: ce7ef3b3
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2972.742 ; gain = 0.000 ; free physical = 1993 ; free virtual = 25266
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2972.742 ; gain = 0.000 ; free physical = 1993 ; free virtual = 25266
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e932fe7b
Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 2972.742 ; gain = 0.000 ; free physical = 1987 ; free virtual = 25261
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1a232c076
Time (s): cpu = 00:00:24 ; elapsed = 00:00:13 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1938 ; free virtual = 25212
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1a232c076
Time (s): cpu = 00:00:24 ; elapsed = 00:00:13 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1938 ; free virtual = 25212
Phase 1 Placer Initialization | Checksum: 1a232c076
Time (s): cpu = 00:00:24 ; elapsed = 00:00:13 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1938 ; free virtual = 25212
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1714329df
Time (s): cpu = 00:00:31 ; elapsed = 00:00:16 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1950 ; free virtual = 25225
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1669c664b
Time (s): cpu = 00:00:36 ; elapsed = 00:00:19 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1948 ; free virtual = 25222
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1669c664b
Time (s): cpu = 00:00:36 ; elapsed = 00:00:19 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1941 ; free virtual = 25215
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: cbaea2ff
Time (s): cpu = 00:02:25 ; elapsed = 00:01:13 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1605 ; free virtual = 24890
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 327 LUTNM shape to break, 137 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 79, two critical 248, total 327, new lutff created 7
INFO: [Physopt 32-1138] End 1 Pass. Optimized 379 nets or LUTs. Breaked 327 LUTs, combined 52 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.770 ; gain = 0.000 ; free physical = 1604 ; free virtual = 24889
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 327 | 52 | 379 | 0 | 1 | 00:00:01 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 327 | 52 | 379 | 0 | 9 | 00:00:02 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: b910804f
Time (s): cpu = 00:02:34 ; elapsed = 00:01:19 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1604 ; free virtual = 24889
Phase 2.4 Global Placement Core | Checksum: 15db7ce53
Time (s): cpu = 00:03:50 ; elapsed = 00:01:49 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1605 ; free virtual = 24890
Phase 2 Global Placement | Checksum: 15db7ce53
Time (s): cpu = 00:03:50 ; elapsed = 00:01:49 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1605 ; free virtual = 24890
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: a8bac4ac
Time (s): cpu = 00:03:56 ; elapsed = 00:01:52 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1610 ; free virtual = 24895
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: ee11d24e
Time (s): cpu = 00:04:07 ; elapsed = 00:01:59 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1597 ; free virtual = 24882
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1372f8fed
Time (s): cpu = 00:04:08 ; elapsed = 00:02:00 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1595 ; free virtual = 24880
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: b1147ddb
Time (s): cpu = 00:04:08 ; elapsed = 00:02:00 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1595 ; free virtual = 24880
Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 14656a765
Time (s): cpu = 00:04:32 ; elapsed = 00:02:15 . Memory (MB): peak = 2979.770 ; gain = 7.027 ; free physical = 1593 ; free virtual = 24878
Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1114a76aa
Time (s): cpu = 00:04:46 ; elapsed = 00:02:28 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1604 ; free virtual = 24889
Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: a807575e
Time (s): cpu = 00:04:49 ; elapsed = 00:02:31 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1600 ; free virtual = 24885
Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 121a753ff
Time (s): cpu = 00:04:49 ; elapsed = 00:02:31 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1600 ; free virtual = 24885
Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 18a56e632
Time (s): cpu = 00:05:22 ; elapsed = 00:02:52 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1602 ; free virtual = 24887
Phase 3 Detail Placement | Checksum: 18a56e632
Time (s): cpu = 00:05:23 ; elapsed = 00:02:53 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1602 ; free virtual = 24888
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: d565a77c
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-5.898 | TNS=-9237.126 |
Phase 1 Physical Synthesis Initialization | Checksum: 1956adfc8
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2987.773 ; gain = 0.000 ; free physical = 1622 ; free virtual = 24907
INFO: [Place 46-33] Processed net Controller/Interpreter/reset_core, BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1956adfc8
Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2987.773 ; gain = 0.000 ; free physical = 1599 ; free virtual = 24893
Phase 4.1.1.1 BUFG Insertion | Checksum: d565a77c
Time (s): cpu = 00:05:49 ; elapsed = 00:03:07 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1590 ; free virtual = 24896
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=-4.690. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1041b176c
Time (s): cpu = 00:07:47 ; elapsed = 00:04:59 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1572 ; free virtual = 24889
Time (s): cpu = 00:07:47 ; elapsed = 00:04:59 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1572 ; free virtual = 24889
Phase 4.1 Post Commit Optimization | Checksum: 1041b176c
Time (s): cpu = 00:07:47 ; elapsed = 00:04:59 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1572 ; free virtual = 24889
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1041b176c
Time (s): cpu = 00:07:47 ; elapsed = 00:04:59 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1572 ; free virtual = 24889
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 4x4|
|___________|___________________|___________________|
| South| 1x1| 4x4|
|___________|___________________|___________________|
| East| 8x8| 16x16|
|___________|___________________|___________________|
| West| 4x4| 4x4|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1041b176c
Time (s): cpu = 00:07:48 ; elapsed = 00:05:00 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1572 ; free virtual = 24889
Phase 4.3 Placer Reporting | Checksum: 1041b176c
Time (s): cpu = 00:07:48 ; elapsed = 00:05:00 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1566 ; free virtual = 24883
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2987.773 ; gain = 0.000 ; free physical = 1565 ; free virtual = 24881
Time (s): cpu = 00:07:48 ; elapsed = 00:05:00 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1565 ; free virtual = 24881
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 117f84ed2
Time (s): cpu = 00:07:48 ; elapsed = 00:05:00 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1564 ; free virtual = 24880
Ending Placer Task | Checksum: 102d92129
Time (s): cpu = 00:07:48 ; elapsed = 00:05:00 . Memory (MB): peak = 2987.773 ; gain = 15.031 ; free physical = 1566 ; free virtual = 24882
38 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:07:52 ; elapsed = 00:05:02 . Memory (MB): peak = 2987.773 ; gain = 47.047 ; free physical = 1565 ; free virtual = 24881
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2987.773 ; gain = 0.000 ; free physical = 1565 ; free virtual = 24881
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2987.773 ; gain = 0.000 ; free physical = 1566 ; free virtual = 24882
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: c8cf3bca ConstDB: 0 ShapeSum: 3a09e55f RouteDB: 0
Post Restoration Checksum: NetGraph: 66915637 | NumContArr: f436d54e | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2e01a20bf
Time (s): cpu = 00:01:33 ; elapsed = 00:01:14 . Memory (MB): peak = 2987.773 ; gain = 0.000 ; free physical = 1876 ; free virtual = 25237
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2e01a20bf
Time (s): cpu = 00:01:34 ; elapsed = 00:01:14 . Memory (MB): peak = 2987.773 ; gain = 0.000 ; free physical = 1877 ; free virtual = 25237
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2e01a20bf
Time (s): cpu = 00:01:34 ; elapsed = 00:01:14 . Memory (MB): peak = 2987.773 ; gain = 0.000 ; free physical = 1877 ; free virtual = 25237
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2f7c05801
Time (s): cpu = 00:02:02 ; elapsed = 00:01:29 . Memory (MB): peak = 2987.773 ; gain = 0.000 ; free physical = 1760 ; free virtual = 25120
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.150 | TNS=-6171.895| WHS=-0.776 | THS=-2033.627|
Router Utilization Summary
Global Vertical Routing Utilization = 0.0186708 %
Global Horizontal Routing Utilization = 0.0126456 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 13114
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 13078
Number of Partially Routed Nets = 36
Number of Node Overlaps = 27
Phase 2 Router Initialization | Checksum: 3170d0476
Time (s): cpu = 00:02:13 ; elapsed = 00:01:34 . Memory (MB): peak = 2987.773 ; gain = 0.000 ; free physical = 1703 ; free virtual = 25063
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 3170d0476
Time (s): cpu = 00:02:13 ; elapsed = 00:01:34 . Memory (MB): peak = 2987.773 ; gain = 0.000 ; free physical = 1703 ; free virtual = 25063
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 2cc3ffab5
Time (s): cpu = 00:03:20 ; elapsed = 00:02:09 . Memory (MB): peak = 3037.754 ; gain = 49.980 ; free physical = 1540 ; free virtual = 24913
Phase 3 Initial Routing | Checksum: 2cc3ffab5
Time (s): cpu = 00:03:20 ; elapsed = 00:02:09 . Memory (MB): peak = 3037.754 ; gain = 49.980 ; free physical = 1540 ; free virtual = 24913
INFO: [Route 35-580] Design has 550 pins with tight setup and hold constraints.
The top 5 pins with tight setup and hold constraints:
+====================+===================+=====================================+
| Launch Setup Clock | Launch Hold Clock | Pin |
+====================+===================+=====================================+
| sys_clk_pin | sys_clk_pin | u_dut/u_lsu/mem_data_wr_q_reg[23]/D |
| sys_clk_pin | sys_clk_pin | u_dut/u_lsu/mem_data_wr_q_reg[7]/D |
| sys_clk_pin | sys_clk_pin | u_dut/u_lsu/mem_data_wr_q_reg[15]/D |
| sys_clk_pin | sys_clk_pin | u_dut/u_lsu/mem_data_wr_q_reg[8]/D |
| sys_clk_pin | sys_clk_pin | u_dut/u_lsu/mem_data_wr_q_reg[10]/D |
+--------------------+-------------------+-------------------------------------+
File with complete list of pins: tight_setup_hold_pins.txt
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 7156
Number of Nodes with overlaps = 2504
Number of Nodes with overlaps = 1113
Number of Nodes with overlaps = 529
Number of Nodes with overlaps = 304
Number of Nodes with overlaps = 167
Number of Nodes with overlaps = 92
Number of Nodes with overlaps = 59
Number of Nodes with overlaps = 36
Number of Nodes with overlaps = 26
Number of Nodes with overlaps = 20
Number of Nodes with overlaps = 9
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 8
Number of Nodes with overlaps = 7
Number of Nodes with overlaps = 8
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-6.627 | TNS=-13909.533| WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 2dc30c29c
Time (s): cpu = 00:16:01 ; elapsed = 00:12:21 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1757 ; free virtual = 25244
Phase 4.2 Global Iteration 1
Number of Nodes with overlaps = 1522
Number of Nodes with overlaps = 983
Number of Nodes with overlaps = 666
Number of Nodes with overlaps = 364
Number of Nodes with overlaps = 256
Number of Nodes with overlaps = 157
Number of Nodes with overlaps = 122
Number of Nodes with overlaps = 72
Number of Nodes with overlaps = 41
Number of Nodes with overlaps = 21
Number of Nodes with overlaps = 15
Number of Nodes with overlaps = 7
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-6.520 | TNS=-13714.211| WHS=N/A | THS=N/A |
Phase 4.2 Global Iteration 1 | Checksum: 20c207473
Time (s): cpu = 00:22:07 ; elapsed = 00:16:11 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1732 ; free virtual = 25220
Phase 4.3 Global Iteration 2
Number of Nodes with overlaps = 785
Phase 4.3 Global Iteration 2 | Checksum: 2e0e0d626
Time (s): cpu = 00:22:09 ; elapsed = 00:16:13 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1738 ; free virtual = 25226
Phase 4 Rip-up And Reroute | Checksum: 2e0e0d626
Time (s): cpu = 00:22:09 ; elapsed = 00:16:13 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1739 ; free virtual = 25227
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 2f4455606
Time (s): cpu = 00:22:15 ; elapsed = 00:16:16 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1744 ; free virtual = 25232
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-6.513 | TNS=-13541.967| WHS=N/A | THS=N/A |
Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 1c93e7784
Time (s): cpu = 00:22:16 ; elapsed = 00:16:16 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1737 ; free virtual = 25225
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1c93e7784
Time (s): cpu = 00:22:16 ; elapsed = 00:16:16 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1736 ; free virtual = 25224
Phase 5 Delay and Skew Optimization | Checksum: 1c93e7784
Time (s): cpu = 00:22:16 ; elapsed = 00:16:16 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1734 ; free virtual = 25221
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 16e30cb44
Time (s): cpu = 00:22:23 ; elapsed = 00:16:20 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1731 ; free virtual = 25218
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-6.463 | TNS=-13481.828| WHS=0.022 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 17438a52d
Time (s): cpu = 00:22:23 ; elapsed = 00:16:20 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1732 ; free virtual = 25220
Phase 6 Post Hold Fix | Checksum: 17438a52d
Time (s): cpu = 00:22:24 ; elapsed = 00:16:20 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1732 ; free virtual = 25220
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 6.58237 %
Global Horizontal Routing Utilization = 7.98693 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
--GLOBAL Congestion:
Utilization threshold used for congestion level computation: 0.85
Congestion Report
North Dir 1x1 Area, Max Cong = 98.1982%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
INT_R_X41Y98 -> INT_R_X41Y98
INT_R_X33Y97 -> INT_R_X33Y97
INT_R_X29Y96 -> INT_R_X29Y96
INT_R_X29Y95 -> INT_R_X29Y95
INT_R_X33Y95 -> INT_R_X33Y95
South Dir 1x1 Area, Max Cong = 99.0991%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
INT_R_X33Y85 -> INT_R_X33Y85
INT_R_X31Y84 -> INT_R_X31Y84
INT_L_X34Y83 -> INT_L_X34Y83
INT_R_X43Y83 -> INT_R_X43Y83
INT_R_X31Y82 -> INT_R_X31Y82
East Dir 8x8 Area, Max Cong = 88.9247%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
INT_L_X24Y88 -> INT_R_X31Y95
INT_L_X24Y80 -> INT_R_X31Y87
West Dir 2x2 Area, Max Cong = 94.4853%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
INT_L_X34Y86 -> INT_R_X35Y87
INT_L_X34Y84 -> INT_R_X35Y85
INT_L_X36Y84 -> INT_R_X37Y85
INT_L_X34Y82 -> INT_R_X35Y83
INT_L_X36Y82 -> INT_R_X37Y83
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 1 Aspect Ratio: 1 Sparse Ratio: 1.25
Direction: East
----------------
Congested clusters found at Level 2
Effective congestion level: 4 Aspect Ratio: 0.4 Sparse Ratio: 0.5625
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 2 Aspect Ratio: 0.75 Sparse Ratio: 2.8125
Phase 7 Route finalize | Checksum: 17438a52d
Time (s): cpu = 00:22:24 ; elapsed = 00:16:20 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1734 ; free virtual = 25221
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 17438a52d
Time (s): cpu = 00:22:24 ; elapsed = 00:16:20 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1732 ; free virtual = 25220
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 18fc9f6e7
Time (s): cpu = 00:22:30 ; elapsed = 00:16:25 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1741 ; free virtual = 25229
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=-6.463 | TNS=-13481.828| WHS=0.022 | THS=0.000 |
WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 10 Post Router Timing | Checksum: 18fc9f6e7
Time (s): cpu = 00:22:35 ; elapsed = 00:16:26 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1749 ; free virtual = 25237
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: ed9a582a
Time (s): cpu = 00:22:37 ; elapsed = 00:16:28 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1755 ; free virtual = 25243
Ending Routing Task | Checksum: ed9a582a
Time (s): cpu = 00:22:38 ; elapsed = 00:16:29 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1755 ; free virtual = 25243
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:22:44 ; elapsed = 00:16:33 . Memory (MB): peak = 3109.754 ; gain = 121.980 ; free physical = 1755 ; free virtual = 25243
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (0)
------------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (1)
-------------------------------
There is 1 port with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
-6.462 -13473.673 5748 28766 0.023 0.000 0 28766 3.750 0.000 0 7730
Timing constraints are not met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin -6.462 -12970.880 5252 23747 0.023 0.000 0 23747 3.750 0.000 0 7730
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
**async_default** sys_clk_pin sys_clk_pin -2.301 -502.793 496 5019 0.205 0.000 0 5019
report_timing_summary: Time (s): cpu = 00:00:23 ; elapsed = 00:00:08 . Memory (MB): peak = 3109.754 ; gain = 0.000 ; free physical = 1751 ; free virtual = 25239
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/biriscv/biriscv/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 3141.770 ; gain = 8.004 ; free physical = 1745 ; free virtual = 25233
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
report_timing_summary: Time (s): cpu = 00:00:16 ; elapsed = 00:00:05 . Memory (MB): peak = 3141.770 ; gain = 0.000 ; free physical = 1747 ; free virtual = 25234
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 3165.781 ; gain = 24.012 ; free physical = 1722 ; free virtual = 25210
# write_bitstream -force "digilent_nexys4_ddr.bit"
Command: write_bitstream -force digilent_nexys4_ddr.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC DPIP-1] Input pipelining: DSP u_dut/u_mul/mult_result_w input u_dut/u_mul/mult_result_w/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP u_dut/u_mul/mult_result_w input u_dut/u_mul/mult_result_w/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP u_dut/u_mul/mult_result_w__0 input u_dut/u_mul/mult_result_w__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP u_dut/u_mul/mult_result_w__0 input u_dut/u_mul/mult_result_w__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP u_dut/u_mul/mult_result_w__1 input u_dut/u_mul/mult_result_w__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP u_dut/u_mul/mult_result_w__1 input u_dut/u_mul/mult_result_w__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP u_dut/u_mul/mult_result_w__2 input u_dut/u_mul/mult_result_w__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP u_dut/u_mul/mult_result_w output u_dut/u_mul/mult_result_w/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP u_dut/u_mul/mult_result_w__0 output u_dut/u_mul/mult_result_w__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP u_dut/u_mul/mult_result_w__1 output u_dut/u_mul/mult_result_w__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP u_dut/u_mul/mult_result_w__2 output u_dut/u_mul/mult_result_w__2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP u_dut/u_mul/mult_result_w multiplier stage u_dut/u_mul/mult_result_w/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP u_dut/u_mul/mult_result_w__0 multiplier stage u_dut/u_mul/mult_result_w__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP u_dut/u_mul/mult_result_w__1 multiplier stage u_dut/u_mul/mult_result_w__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP u_dut/u_mul/mult_result_w__2 multiplier stage u_dut/u_mul/mult_result_w__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 16 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_nexys4_ddr.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 16 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:51 ; elapsed = 00:00:38 . Memory (MB): peak = 3301.145 ; gain = 135.363 ; free physical = 1534 ; free virtual = 25026
INFO: [Common 17-206] Exiting Vivado at Tue Nov 12 04:10:43 2024...
![[Jenkins]](/jenkins/static/ee6d6826/images/svgs/logo.svg){kind=logo}
