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Start of Pipeline - (6 min 50 sec in block)
node - (6 min 45 sec in block)
node block - (6 min 43 sec in block)
stage - (2.7 sec in block)Git Clone
stage block (Git Clone) - (2.1 sec in block)
sh - (0.54 sec in self)rm -rf biriscv
sh - (1.2 sec in self)git clone --recursive https://github.com/ultraembedded/biriscv biriscv
stage - (2.3 sec in block)Simulation
stage block (Simulation) - (1.5 sec in block)
dir - (1 sec in block)biriscv
dir block - (0.71 sec in block)
sh - (0.44 sec in self)iverilog -o simulation.out -g2005 -s riscv_core -I src/core src/core/biriscv_alu.v src/core/biriscv_csr.v src/core/biriscv_csr_regfile.v src/core/biriscv_decode.v src/core/biriscv_decoder.v src/core/biriscv_defs.v src/core/biriscv_divider.v src/core/biriscv_exec.v src/core/biriscv_fetch.v src/core/biriscv_frontend.v src/core/biriscv_issue.v src/core/biriscv_lsu.v src/core/biriscv_mmu.v src/core/biriscv_multiplier.v src/core/biriscv_npc.v src/core/biriscv_pipe_ctrl.v src/core/biriscv_regfile.v src/core/biriscv_trace_sim.v src/core/biriscv_xilinx_2r1w.v src/core/riscv_core.v
stage - (6 min 36 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (6 min 35 sec in block)
parallel - (6 min 34 sec in block)
parallel block (Branch: colorlight_i9) - (57 ms in block)
stage - (13 sec in block)colorlight_i9
stage block (colorlight_i9) - (13 sec in block)
lock - (12 sec in block)colorlight_i9
lock block - (11 sec in block)
stage - (8.7 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (7.9 sec in block)
dir - (6.9 sec in block)biriscv
dir block - (6.6 sec in block)
echo - (0.2 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (5.9 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p biriscv -b colorlight_i9
stage - (1.2 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.59 sec in block)
getContext - (0.25 sec in self)
stage - (0.88 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.41 sec in block)
getContext - (0.17 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (6 min 33 sec in block)
stage - (6 min 32 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (6 min 31 sec in block)
lock - (6 min 30 sec in block)digilent_nexys4_ddr
lock block - (6 min 28 sec in block)
stage - (6 min 24 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (6 min 23 sec in block)
dir - (6 min 22 sec in block)biriscv
dir block - (6 min 22 sec in block)
echo - (0.17 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (6 min 21 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p biriscv -b digilent_nexys4_ddr
stage - (1.5 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.48 sec in block)
getContext - (0.25 sec in self)
stage - (1.4 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.83 sec in block)
getContext - (0.39 sec in self)
stage - (1.6 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.1 sec in block)
junit - (0.64 sec in self)**/test-reports/*.xml