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Start of Pipeline - (47 min in block)
node - (47 min in block)
node block - (47 min in block)
stage - (2.4 sec in block)Git Clone
stage block (Git Clone) - (1.9 sec in block)
sh - (0.46 sec in self)rm -rf biriscv
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/ultraembedded/biriscv biriscv
stage - (1.9 sec in block)Simulation
stage block (Simulation) - (1.3 sec in block)
dir - (0.92 sec in block)biriscv
dir block - (0.65 sec in block)
sh - (0.43 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s riscv_core -I src/core src/core/biriscv_alu.v src/core/biriscv_csr.v src/core/biriscv_csr_regfile.v src/core/biriscv_decode.v src/core/biriscv_decoder.v src/core/biriscv_defs.v src/core/biriscv_divider.v src/core/biriscv_exec.v src/core/biriscv_fetch.v src/core/biriscv_frontend.v src/core/biriscv_issue.v src/core/biriscv_lsu.v src/core/biriscv_mmu.v src/core/biriscv_multiplier.v src/core/biriscv_npc.v src/core/biriscv_pipe_ctrl.v src/core/biriscv_regfile.v src/core/biriscv_trace_sim.v src/core/biriscv_xilinx_2r1w.v src/core/riscv_core.v
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.3 sec in block)
dir - (0.91 sec in block)biriscv
dir block - (0.66 sec in block)
sh - (0.43 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (47 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (47 min in block)
parallel - (47 min in block)
parallel block (Branch: colorlight_i9) - (50 ms in block)
stage - (47 min in block)colorlight_i9
stage block (colorlight_i9) - (47 min in block)
lock - (47 min in block)colorlight_i9
lock block - (47 min in block)
stage - (47 min in block)Synthesis and PnR
stage block (Synthesis and PnR) - (47 min in block)
dir - (47 min in block)biriscv
dir block - (47 min in block)
echo - (0.15 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (47 min in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p biriscv -b colorlight_i9
stage - (28 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (27 sec in block)
dir - (27 sec in block)biriscv
dir block - (27 sec in block)
echo - (0.16 sec in self)Flashing FPGA colorlight_i9.
sh - (26 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p biriscv -b colorlight_i9 -l
stage - (2 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.8 sec in block)
echo - (0.2 sec in self)Testing FPGA colorlight_i9.
dir - (1.3 sec in block)biriscv
dir block - (1 sec in block)
sh - (0.44 sec in self)echo "Test for FPGA in /dev/ttyACM0"
sh - (0.39 sec in self)python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0
parallel block (Branch: digilent_arty_a7_100t) - (45 min in block)
stage - (45 min in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (45 min in block)
lock - (45 min in block)digilent_arty_a7_100t
lock block - (41 min in block)
stage - (41 min in block)Synthesis and PnR
stage block (Synthesis and PnR) - (41 min in block)
dir - (41 min in block)biriscv
dir block - (41 min in block)
echo - (0.33 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (41 min in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p biriscv -b digilent_arty_a7_100t
stage - (5.2 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.7 sec in block)
dir - (4.3 sec in block)biriscv
dir block - (4.1 sec in block)
echo - (0.16 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.7 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p biriscv -b digilent_arty_a7_100t -l
stage - (2.1 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (1.8 sec in block)
echo - (0.21 sec in self)Testing FPGA digilent_arty_a7_100t.
dir - (1.3 sec in block)biriscv
dir block - (1 sec in block)
sh - (0.45 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (0.42 sec in self)python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1
stage - (1.4 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1 sec in block)
junit - (0.51 sec in self)**/test-reports/*.xml