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Start of Pipeline - (14 sec in block)
node - (13 sec in block)
node block - (12 sec in block)
stage - (2.9 sec in block)Git Clone
stage block (Git Clone) - (2.4 sec in block)
sh - (0.48 sec in self)rm -rf *.xml
sh - (0.46 sec in self)rm -rf arRISCado
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/arRISCado/arRISCado arRISCado
stage - (2 sec in block)Simulation
stage block (Simulation) - (1.4 sec in block)
dir - (0.97 sec in block)arRISCado
dir block - (0.67 sec in block)
sh - (0.46 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s cpu project/cpu.v project/flash.v project/mmu.v project/ram.v project/rom.v project/top.v project/uart.v project/cpu/alu.v project/cpu/decode.v project/cpu/divider.v project/cpu/execute.v project/cpu/fetch.v project/cpu/memory.v project/cpu/register_bank.v project/cpu/writeback.v project/peripheral/buttons.v project/peripheral/peripheral_manager.v project/peripheral/pwm_port.v
stage - (0.95 sec in block)Utilities
stage block (Utilities) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (5.7 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5.1 sec in block)
getContext - (0.27 sec in self)
parallel - (4.4 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4.1 sec in block)
stage - (3.6 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3.3 sec in block)
getContext - (0.38 sec in self)
stage - (0.91 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (0.97 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.39 sec in block)
getContext - (0.17 sec in self)
stage - (0.71 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.4 sec in block)
getContext - (0.17 sec in self)
stage - (0.72 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.51 sec in block)
junit - (0.25 sec in self)**/*.xml