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Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/airisc_core_complex
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf *.xml
[Pipeline] sh
+ rm -rf airisc_core_complex
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/Fraunhofer-IMS/airisc_core_complex airisc_core_complex
Cloning into 'airisc_core_complex'...
Submodule 'external/elf2hex' (https://github.com/sifive/elf2hex.git) registered for path 'external/elf2hex'
Submodule 'external/neoTRNG' (https://github.com/stnolting/neoTRNG.git) registered for path 'external/neoTRNG'
Submodule 'external/riscv-tests' (https://github.com/riscv-software-src/riscv-tests.git) registered for path 'external/riscv-tests'
Cloning into '/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/external/elf2hex'...
Cloning into '/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/external/neoTRNG'...
Cloning into '/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/external/riscv-tests'...
Submodule path 'external/elf2hex': checked out 'f28a3103c06131ed3895052b1341daf4ca0b1c9c'
Submodule path 'external/neoTRNG': checked out '9889e484295b47b8d12972f732e126b26d0da7de'
Submodule path 'external/riscv-tests': checked out '96403c8facf128564e7828d37daee948147bfad0'
Submodule 'env' (https://github.com/riscv/riscv-test-env.git) registered for path 'external/riscv-tests/env'
Cloning into '/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/external/riscv-tests/env'...
Submodule path 'external/riscv-tests/env': checked out '4fabfb4e0d3eacc1dc791da70e342e4b68ea7e46'
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex
[Pipeline] {
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s airi5c_core -I src/ -I src/modules/airi5c_mul_div/src/ -I src/modules/airi5c_fpu/ src/airi5c_core.v src/airi5c_PC_mux.v src/airi5c_sync_to_hasti_bridge.v src/airi5c_alu.v src/airi5c_ctrl.v src/airi5c_dpsram_4x8to32bit_wrapper.v src/airi5c_periph_mux.v src/airi5c_WB_pregs.v src/airi5c_debug_module.v src/airi5c_EX_pregs.v src/airi5c_pipeline.v src/airi5c_wb_src_mux.v src/airi5c_branch_prediction.v src/airi5c_debug_rom.v src/airi5c_fetch.v src/airi5c_prebuf_fifo.v src/airi5c_decode.v src/airi5c_regfile.v src/airi5c_decompression.v src/airi5c_imm_gen.v src/airi5c_src_a_mux.v src/airi5c_csr_file.v src/airi5c_dmem_latch.v src/airi5c_mem_arbiter.v src/airi5c_src_b_mux.v src/modules/airi5c_mul_div/src/airi5c_mul_div.v src/modules/airi5c_fpu/airi5c_classifier.v src/modules/airi5c_fpu/airi5c_float_divider.v src/modules/airi5c_fpu/airi5c_FPU.v src/modules/airi5c_fpu/airi5c_leading_zero_counter_4.v src/modules/airi5c_fpu/airi5c_rshifter.v src/modules/airi5c_fpu/airi5c_float_adder.v src/modules/airi5c_fpu/airi5c_float_multiplier.v src/modules/airi5c_fpu/airi5c_ftoi_converter.v src/modules/airi5c_fpu/airi5c_post_processing.v src/modules/airi5c_fpu/airi5c_selector.v src/modules/airi5c_fpu/airi5c_float_arithmetic.v src/modules/airi5c_fpu/airi5c_float_sqrt.v src/modules/airi5c_fpu/airi5c_itof_converter.v src/modules/airi5c_fpu/airi5c_pre_normalizer.v src/modules/airi5c_fpu/airi5c_sign_modifier.v src/modules/airi5c_fpu/airi5c_float_comparator_comb.v src/modules/airi5c_fpu/airi5c_FPU_constants.vh src/modules/airi5c_fpu/airi5c_leading_zero_counter_24.v src/modules/airi5c_fpu/airi5c_rounding_logic.v src/modules/airi5c_fpu/airi5c_splitter.v src/modules/airi5c_fpu/airi5c_float_comparator_seq.v src/modules/airi5c_fpu/airi5c_FPU_core.v src/modules/airi5c_fpu/airi5c_leading_zero_counter_32.v src/modules/airi5c_fpu/airi5c_rshifter_static.v
src/airi5c_core.v:171: warning: Port 28 (dm_state_out) of airi5c_debug_module expects 4 bits, got 5.
src/airi5c_core.v:171:        : Padding 1 high bits of the expression.
src/airi5c_fetch.v:231: warning: Port 8 (re_i) of airi5c_prebuf_fifo expects 3 bits, got 1.
src/airi5c_fetch.v:231:        : Padding 2 high bits of the port.
src/airi5c_fetch.v:248: warning: Port 8 (re_i) of airi5c_prebuf_fifo expects 3 bits, got 1.
src/airi5c_fetch.v:248:        : Padding 2 high bits of the port.
src/airi5c_pipeline.v:483: warning: Port 11 (error_in_if_o) of airi5c_fetch expects 3 bits, got 1.
src/airi5c_pipeline.v:483:        : Padding 2 high bits of the port.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
Trying to read file: /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/src/airi5c_core.v
Cache-related signals in airi5c_prebuf_fifo.v
Cache-related signals in airi5c_fetch.v
Cache-related signals in airi5c_uart.v
Cache-related signals in airi5c_trng.v
Cache-related signals in airi5c_spi.v
Cache-related signals in airi5c_ftoi_converter.v
Results saved to /jenkins/processor_ci_utils/labels/airisc_core_complex.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
Resource [digilent_arty_a7_100t] did not exist. Created.
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p airisc_core_complex -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Common 17-69] Command failed: File '/eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv' does not exist
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 296, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_arty_a7_100t
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: c4fce44d-9dd0-4f12-990e-68529ce25206
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE