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Start of Pipeline - (32 sec in block)
node - (31 sec in block)
node block - (30 sec in block)
stage - (2 sec in block)Git Clone
stage block (Git Clone) - (0.91 sec in block)
sh - (0.47 sec in self)rm -rf VexRiscv
stage - (1.9 sec in block)Verilog Convert
stage block (Verilog Convert) - (0.76 sec in block)
getContext - (0.32 sec in self)
stage - (1.9 sec in block)Simulation
stage block (Simulation) - (0.76 sec in block)
getContext - (0.34 sec in self)
stage - (19 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (18 sec in block)
getContext - (0.57 sec in self)
parallel - (16 sec in block)
parallel block (Branch: colorlight_i9) - (0.11 sec in block)
stage - (13 sec in block)colorlight_i9
stage block (colorlight_i9) - (13 sec in block)
getContext - (1.3 sec in self)
stage - (3.6 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (1.2 sec in block)
getContext - (0.35 sec in self)
stage - (3.7 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (1.2 sec in block)
getContext - (0.39 sec in self)
stage - (2.7 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (1.3 sec in block)
getContext - (0.35 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (15 sec in block)
stage - (13 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (12 sec in block)
getContext - (1.2 sec in self)
stage - (3.6 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (1.5 sec in block)
getContext - (0.38 sec in self)
stage - (3.6 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (1.5 sec in block)
getContext - (0.38 sec in self)
stage - (2.7 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (1.5 sec in block)
getContext - (0.38 sec in self)
stage - (4.6 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (4.4 sec in block)
junit - (3.5 sec in self)**/test-reports/*.xml