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VexRiscv
#1
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Status
Start of Pipeline - (20 sec in block)
node - (20 sec in block)
node block - (19 sec in block)
stage - (4.8 sec in block)
Git Clone
stage block (Git Clone) - (4.3 sec in block)
sh - (0.48 sec in self)
rm -rf VexRiscv
sh - (3.6 sec in self)
git clone --recursive https://github.com/SpinalHDL/VexRiscv VexRiscv
stage - (2 sec in block)
Verilog Convert
stage block (Verilog Convert) - (1.4 sec in block)
dir - (0.96 sec in block)
VexRiscv
dir block - (0.68 sec in block)
sh - (0.46 sec in self)
sbt "runMain vexriscv.demo.GenFull"
stage - (0.93 sec in block)
Simulation
stage block (Simulation) - (0.34 sec in block)
getContext - (0.16 sec in self)
stage - (9.8 sec in block)
FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (9.2 sec in block)
getContext - (0.25 sec in self)
parallel - (8.5 sec in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (7.1 sec in block)
colorlight_i9
stage block (colorlight_i9) - (6.6 sec in block)
getContext - (0.72 sec in self)
stage - (1.8 sec in block)
Síntese e PnR
stage block (Síntese e PnR) - (0.62 sec in block)
getContext - (0.19 sec in self)
stage - (1.8 sec in block)
Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.74 sec in block)
getContext - (0.2 sec in self)
stage - (1.2 sec in block)
Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.57 sec in block)
getContext - (0.13 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (7.9 sec in block)
stage - (7.1 sec in block)
digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (6.5 sec in block)
getContext - (0.61 sec in self)
stage - (1.9 sec in block)
Síntese e PnR
stage block (Síntese e PnR) - (0.76 sec in block)
getContext - (0.16 sec in self)
stage - (1.8 sec in block)
Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.79 sec in block)
getContext - (0.16 sec in self)
stage - (1.3 sec in block)
Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.7 sec in block)
getContext - (0.18 sec in self)
stage - (1.5 sec in block)
Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.3 sec in block)
dir - (0.9 sec in block)
VexRiscv
dir block - (0.66 sec in block)
sh - (0.42 sec in self)
rm -rf *