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Start of Pipeline - (1 min 3 sec in block)
node - (1 min 2 sec in block)
node block - (1 min 1 sec in block)
stage - (3.6 sec in block)Git Clone
stage block (Git Clone) - (2.9 sec in block)
sh - (0.68 sec in self)rm -rf Taiga
sh - (1.9 sec in self)git clone --recursive --depth=1 https://gitlab.com/sfu-rcl/Taiga Taiga
stage - (2.4 sec in block)Simulation
stage block (Simulation) - (1.5 sec in block)
dir - (1 sec in block)Taiga
dir block - (0.6 sec in block)
echo - (0.2 sec in self)simulation not supported for System Verilog files
stage - (2.9 sec in block)Utilities
stage block (Utilities) - (2.1 sec in block)
dir - (1.3 sec in block)Taiga
dir block - (0.94 sec in block)
sh - (0.53 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (51 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (50 sec in block)
parallel - (50 sec in block)
parallel block (Branch: colorlight_i9) - (0.1 sec in block)
stage - (35 sec in block)colorlight_i9
stage block (colorlight_i9) - (35 sec in block)
lock - (34 sec in block)colorlight_i9
lock block - (33 sec in block)
stage - (30 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (29 sec in block)
dir - (28 sec in block)Taiga
dir block - (28 sec in block)
echo - (0.33 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (26 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Taiga -b colorlight_i9
stage - (0.97 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.7 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.35 sec in block)
getContext - (0.15 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (49 sec in block)
stage - (48 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (47 sec in block)
lock - (46 sec in block)digilent_arty_a7_100t
lock block - (45 sec in block)
stage - (42 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (41 sec in block)
dir - (40 sec in block)Taiga
dir block - (40 sec in block)
echo - (0.36 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (39 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Taiga -b digilent_arty_a7_100t
stage - (0.98 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.15 sec in self)
stage - (0.68 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (0.81 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.58 sec in block)
junit - (0.3 sec in self)**/test-reports/*.xml