Console Output

+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Taiga -b digilent_arty_a7_100t
Final configuration file generated at /var/jenkins_home/workspace/Taiga/Taiga/build_digilent_arty_a7_100t.tcl
Error executing Makefile.
ERROR: [Synth 8-36] 'l2_config_and_types' is not declared [/var/jenkins_home/workspace/Taiga/Taiga/core/axi_to_arb.sv:28]
ERROR: [Synth 8-36] 'L2_ID_W' is not declared [/var/jenkins_home/workspace/Taiga/Taiga/core/axi_to_arb.sv:258]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/Taiga/Taiga/core/axi_to_arb.sv:258]
ERROR: [Synth 8-439] module 'processorci_top' not found
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 307, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.