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Start of Pipeline - (34 sec in block)
node - (33 sec in block)
node block - (32 sec in block)
stage - (4.3 sec in block)Git Clone
stage block (Git Clone) - (3.3 sec in block)
sh - (0.62 sec in self)rm -rf Taiga
sh - (2.3 sec in self)git clone --recursive https://gitlab.com/sfu-rcl/Taiga Taiga
stage - (3.9 sec in block)Simulation
stage block (Simulation) - (2.7 sec in block)
dir - (1.7 sec in block)Taiga
dir block - (1.1 sec in block)
sh - (0.73 sec in self)
stage - (20 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (19 sec in block)
getContext - (0.59 sec in self)
parallel - (17 sec in block)
parallel block (Branch: colorlight_i9) - (0.13 sec in block)
stage - (14 sec in block)colorlight_i9
stage block (colorlight_i9) - (13 sec in block)
getContext - (1.4 sec in self)
stage - (3.6 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (1.2 sec in block)
getContext - (0.37 sec in self)
stage - (3.6 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (1.2 sec in block)
getContext - (0.33 sec in self)
stage - (2.9 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (1.5 sec in block)
getContext - (0.4 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (16 sec in block)
stage - (14 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (13 sec in block)
getContext - (1.3 sec in self)
stage - (3.7 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (1.5 sec in block)
getContext - (0.36 sec in self)
stage - (3.8 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (1.5 sec in block)
getContext - (0.39 sec in self)
stage - (2.7 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (1.6 sec in block)
getContext - (0.44 sec in self)
stage - (2.8 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (2.3 sec in block)
dir - (1.4 sec in block)Taiga
dir block - (0.97 sec in block)
sh - (0.55 sec in self)rm -rf *