Console Output

+ /eda/oss-cad-suite/bin/ghdl -a --std=08 T13x/klessydra-t1-3th/PKG_RiscV_Klessydra.vhd T13x/klessydra-t1-3th/RTL-Accumulator.vhd T13x/klessydra-t1-3th/RTL-CSR_Unit.vhd T13x/klessydra-t1-3th/RTL-Debug_Unit.vhd T13x/klessydra-t1-3th/RTL-DSP_Unit.vhd T13x/klessydra-t1-3th/RTL-Registerfile.vhd T13x/klessydra-t1-3th/RTL-Scratchpad_Memory.vhd T13x/klessydra-t1-3th/RTL-Scratchpad_Memory_Interface.vhd T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd T13x/klessydra-t1-3th/RTL-IF_STAGE.vhd T13x/klessydra-t1-3th/RTL-ID_STAGE.vhd T13x/klessydra-t1-3th/RTL-IE_STAGE.vhd T13x/klessydra-t1-3th/RTL-Load_Store_Unit.vhd T13x/klessydra-t1-3th/RTL-Processing_Pipeline.vhd T13x/klessydra-t1-3th/STR-Klessydra_top.vhd
T13x/klessydra-t1-3th/RTL-Registerfile.vhd:85:26:error: no "RS1_Data_IE" for attribute specification
  attribute ram_style of RS1_Data_IE        : signal is "reg";
                         ^
T13x/klessydra-t1-3th/RTL-Registerfile.vhd:86:26:error: no "RS2_Data_IE" for attribute specification
  attribute ram_style of RS2_Data_IE        : signal is "reg";
                         ^
T13x/klessydra-t1-3th/RTL-Registerfile.vhd:87:26:error: no "RD_Data_IE" for attribute specification
  attribute ram_style of RD_Data_IE         : signal is "reg";
                         ^
T13x/klessydra-t1-3th/RTL-Registerfile.vhd:265:3:warning: declaration of "RF_FF" hides if generate statement [-Whide]
  RF_FF : if LUTRAM_RF = 0 generate
  ^
T13x/klessydra-t1-3th/RTL-Registerfile.vhd:288:3:warning: declaration of "RF_LUTRAM" hides if generate statement [-Whide]
  RF_LUTRAM : if LUTRAM_RF = 1 generate
  ^
/eda/oss-cad-suite/libexec/ghdl:error: compilation error