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Start of Pipeline - (6 min 44 sec in block)
node - (6 min 43 sec in block)
node block - (6 min 43 sec in block)
stage - (2.4 sec in block)Git Clone and Cleanup
stage block (Git Clone and Cleanup) - (2 sec in block)
sh - (0.47 sec in self)rm -rf T03x
sh - (1.3 sec in self)git clone --recursive https://github.com/klessydra/T03x.git T03x
stage - (9.8 sec in block)Simulation
stage block (Simulation) - (9.3 sec in block)
dir - (9 sec in block)T03x
dir block - (8.7 sec in block)
sh - (8.5 sec in self)/eda/oss-cad-suite/bin/ghdl -a --std=08 klessydra-t0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-t0-3th/PKG_RiscV_Klessydra.vhd klessydra-t0-3th/RTL-CSR_Unit.vhd klessydra-t0-3th/RTL-Debug_Unit.vhd klessydra-t0-3th/RTL-Processing_Pipeline.vhd klessydra-t0-3th/RTL-Program_Counter_unit.vhd klessydra-t0-3th/STR-Klessydra_top.vhd
stage - (6 min 24 sec in block)FPGA Synthesis
stage block (FPGA Synthesis) - (6 min 24 sec in block)
parallel - (6 min 23 sec in block)
parallel block (Branch: colorlight_i9) - (45 ms in block)
stage - (1 min 31 sec in block)colorlight_i9
stage block (colorlight_i9) - (1 min 31 sec in block)
lock - (1 min 30 sec in block)colorlight_i9
lock block - (2.5 sec in block)
echo - (0.41 sec in self)FPGA colorlight_i9 bloqueada para síntese.
dir - (1.6 sec in block)T03x
dir block - (1.2 sec in block)
sh - (0.89 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T03x -b colorlight_i9
parallel block (Branch: digilent_nexys4_ddr) - (6 min 23 sec in block)
stage - (6 min 22 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (6 min 22 sec in block)
lock - (6 min 21 sec in block)digilent_nexys4_ddr
lock block - (1 min 9 sec in block)
echo - (0.47 sec in self)FPGA digilent_nexys4_ddr bloqueada para síntese.
dir - (1 min 8 sec in block)T03x
dir block - (1 min 8 sec in block)
sh - (1 min 8 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T03x -b digilent_nexys4_ddr
stage - (3.9 sec in block)Run Tests
stage block (Run Tests) - (3.3 sec in block)
getContext - (0.26 sec in self)
parallel - (2.7 sec in block)
parallel block (Branch: colorlight_i9 Tests) - (56 ms in block)
stage - (1.3 sec in block)colorlight_i9 Tests
stage block (colorlight_i9 Tests) - (0.66 sec in block)
getContext - (0.22 sec in self)
parallel block (Branch: digilent_nexys4_ddr Tests) - (2 sec in block)
stage - (1.2 sec in block)digilent_nexys4_ddr Tests
stage block (digilent_nexys4_ddr Tests) - (0.83 sec in block)
getContext - (0.22 sec in self)
stage - (1.5 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.3 sec in block)
dir - (0.83 sec in block)T03x
dir block - (0.6 sec in block)
sh - (0.4 sec in self)rm -rf *