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Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/T03x
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone and Cleanup)
[Pipeline] sh
+ rm -rf T03x
[Pipeline] sh
+ git clone --recursive https://github.com/klessydra/T03x.git T03x
Cloning into 'T03x'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/T03x/T03x
[Pipeline] {
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ghdl -a --std=08 klessydra-t0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-t0-3th/PKG_RiscV_Klessydra.vhd klessydra-t0-3th/RTL-CSR_Unit.vhd klessydra-t0-3th/RTL-Debug_Unit.vhd klessydra-t0-3th/RTL-Processing_Pipeline.vhd klessydra-t0-3th/RTL-Program_Counter_unit.vhd klessydra-t0-3th/STR-Klessydra_top.vhd
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:79:12:warning: declaration of "MTVEC" hides port "MTVEC" [-Whide]
    signal MTVEC                     : in    std_logic_vector(31 downto 0);
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:80:12:warning: declaration of "instr_gnt_i" hides port "instr_gnt_i" [-Whide]
    signal instr_gnt_i, taken_branch : in    std_logic;
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:80:25:warning: declaration of "taken_branch" hides port "taken_branch" [-Whide]
    signal instr_gnt_i, taken_branch : in    std_logic;
                        ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:81:12:warning: declaration of "wfi_condition_pending" hides signal "wfi_condition_pending" [-Whide]
    signal wfi_condition_pending     : inout std_logic;
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:82:12:warning: declaration of "set_wfi_condition" hides port "set_wfi_condition" [-Whide]
    signal set_wfi_condition         : in    std_logic;
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:83:12:warning: declaration of "taken_branch_pending" hides port "taken_branch_pending" [-Whide]
    signal taken_branch_pending      : inout std_logic;
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:84:12:warning: declaration of "irq_pending" hides port "irq_pending" [-Whide]
    signal irq_pending               : in    std_logic;
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:85:12:warning: declaration of "set_except_condition" hides port "set_except_condition" [-Whide]
    signal set_except_condition      : in    std_logic;
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:86:12:warning: declaration of "set_mret_condition" hides port "set_mret_condition" [-Whide]
    signal set_mret_condition        : in    std_logic;
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:87:12:warning: declaration of "pc" hides signal "pc" [-Whide]
    signal pc                        : inout std_logic_vector(31 downto 0);
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:88:12:warning: declaration of "taken_branch_pc_lat" hides port "taken_branch_pc_lat" [-Whide]
    signal taken_branch_pc_lat       : in    std_logic_vector(31 downto 0);
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:89:12:warning: declaration of "incremented_pc" hides port "incremented_pc" [-Whide]
    signal incremented_pc            : in    std_logic_vector(31 downto 0);
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:90:12:warning: declaration of "boot_pc" hides signal "boot_pc" [-Whide]
    signal boot_pc                   : in    std_logic_vector(31 downto 0);
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:91:12:warning: declaration of "pc_update_enable" hides signal "pc_update_enable" [-Whide]
    signal pc_update_enable          : in    std_logic;
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:92:12:warning: declaration of "served_except_condition" hides port "served_except_condition" [-Whide]
    signal served_except_condition   : out   std_logic;
           ^
klessydra-t0-3th/RTL-Program_Counter_unit.vhd:93:12:warning: declaration of "served_mret_condition" hides port "served_mret_condition" [-Whide]
    signal served_mret_condition     : out   std_logic) is
           ^
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Synthesis)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
The resource [colorlight_i9] is locked by build Risco 5 #374 #374 since Oct 6, 2024, 2:11 AM.
[Resource: colorlight_i9] is not free, waiting for execution ...
[Required resources: [colorlight_i9]] added into queue at position 0
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_nexys4_ddr]
The resource [digilent_nexys4_ddr] is locked by build Risco 5 #374 #374 since Oct 6, 2024, 2:11 AM.
[Resource: digilent_nexys4_ddr] is not free, waiting for execution ...
[Required resources: [digilent_nexys4_ddr]] added into queue at position 1
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] echo
FPGA colorlight_i9 bloqueada para síntese.
[Pipeline] dir
Running in /var/lib/jenkins/workspace/T03x/T03x
[Pipeline] {
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T03x -b colorlight_i9
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/T03x/T03x/build_colorlight_i9.tcl
Erro ao executar o Makefile.
ERROR: TCL interpreter returned an error: Yosys command produced an error
make: *** [/eda/processor-ci/makefiles/colorlight_i9.mk:13: colorlight_i9.json] Error 1

Traceback (most recent call last):
  File "/eda/processor-ci/main.py", line 248, in <module>
    main(
  File "/eda/processor-ci/main.py", line 196, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor-ci/main.py", line 110, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
Lock acquired on [Resource: digilent_nexys4_ddr]
[Pipeline] {
[Pipeline] echo
FPGA digilent_nexys4_ddr bloqueada para síntese.
[Pipeline] dir
Running in /var/lib/jenkins/workspace/T03x/T03x
[Pipeline] {
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T03x -b digilent_nexys4_ddr
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/T03x/T03x/build_digilent_nexys4_ddr.tcl
Erro ao executar o Makefile.
ERROR: [Synth 8-2757] this construct is only supported in VHDL 1076-2008 [/var/lib/jenkins/workspace/T03x/T03x/klessydra-t0-3th/RTL-CSR_Unit.vhd:891]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor-ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor-ci/main.py", line 248, in <module>
    main(
  File "/eda/processor-ci/main.py", line 196, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor-ci/main.py", line 110, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
Lock released on resource [Resource: digilent_nexys4_ddr]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Run Tests)
Stage "Run Tests" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9 Tests)
[Pipeline] { (Branch: digilent_nexys4_ddr Tests)
[Pipeline] stage
[Pipeline] { (colorlight_i9 Tests)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr Tests)
Stage "colorlight_i9 Tests" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr Tests" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9 Tests
[Pipeline] }
Failed in branch digilent_nexys4_ddr Tests
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/T03x/T03x
[Pipeline] {
[Pipeline] sh
+ rm -rf PKG_RiscV_Klessydra.o PKG_RiscV_Klessydra_thread_parameters.o README.md RTL-CSR_Unit.o RTL-Debug_Unit.o RTL-Processing_Pipeline.o RTL-Program_Counter_unit.o STR-Klessydra_top.o build_colorlight_i9.tcl build_digilent_nexys4_ddr.tcl klessydra-t0-3th pics src_files.yml work-obj08.cf
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE