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Start of Pipeline - (1 min 33 sec in block)
node - (1 min 32 sec in block)
node block - (1 min 31 sec in block)
stage - (2.5 sec in block)Git Clone and Cleanup
stage block (Git Clone and Cleanup) - (1.9 sec in block)
sh - (0.47 sec in self)rm -rf T03x
sh - (1.2 sec in self)git clone --recursive https://github.com/klessydra/T03x.git T03x
stage - (8.8 sec in block)Simulation
stage block (Simulation) - (8.2 sec in block)
dir - (7.8 sec in block)T03x
dir block - (7.6 sec in block)
sh - (7.3 sec in self)/eda/oss-cad-suite/bin/ghdl -a --std=08 klessydra-t0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-t0-3th/PKG_RiscV_Klessydra.vhd klessydra-t0-3th/RTL-CSR_Unit.vhd klessydra-t0-3th/RTL-Debug_Unit.vhd klessydra-t0-3th/RTL-Processing_Pipeline.vhd klessydra-t0-3th/RTL-Program_Counter_unit.vhd klessydra-t0-3th/STR-Klessydra_top.vhd
stage - (1 min 14 sec in block)FPGA Synthesis
stage block (FPGA Synthesis) - (1 min 13 sec in block)
parallel - (1 min 13 sec in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (4.5 sec in block)colorlight_i9
stage block (colorlight_i9) - (4.1 sec in block)
lock - (3.3 sec in block)colorlight_i9
lock block - (2.6 sec in block)
echo - (0.22 sec in self)FPGA colorlight_i9 bloqueada para síntese.
dir - (1.6 sec in block)T03x
dir block - (1.1 sec in block)
sh - (0.52 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T03x -b colorlight_i9
parallel block (Branch: digilent_nexys4_ddr) - (1 min 12 sec in block)
stage - (1 min 11 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (1 min 11 sec in block)
lock - (1 min 10 sec in block)digilent_nexys4_ddr
lock block - (1 min 9 sec in block)
echo - (0.24 sec in self)FPGA digilent_nexys4_ddr bloqueada para síntese.
dir - (1 min 8 sec in block)T03x
dir block - (1 min 8 sec in block)
sh - (1 min 7 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T03x -b digilent_nexys4_ddr
stage - (4.1 sec in block)Run Tests
stage block (Run Tests) - (3.6 sec in block)
getContext - (0.29 sec in self)
parallel - (2.9 sec in block)
parallel block (Branch: colorlight_i9 Tests) - (56 ms in block)
stage - (1.4 sec in block)colorlight_i9 Tests
stage block (colorlight_i9 Tests) - (0.7 sec in block)
getContext - (0.25 sec in self)
parallel block (Branch: digilent_nexys4_ddr Tests) - (2.2 sec in block)
stage - (1.4 sec in block)digilent_nexys4_ddr Tests
stage block (digilent_nexys4_ddr Tests) - (0.88 sec in block)
getContext - (0.22 sec in self)
stage - (1.7 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.4 sec in block)
dir - (0.91 sec in block)T03x
dir block - (0.67 sec in block)
sh - (0.42 sec in self)rm -rf *