Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2031.723 ; gain = 402.660 ; free physical = 5449 ; free virtual = 27777
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WARNING: [Synth 8-10929] literal value 'd8 truncated to fit in 3 bits [/eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv:104]
WARNING: [Synth 8-10929] literal value 'd16 truncated to fit in 3 bits [/eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv:105]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16]
INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/T02x.sv:5]
INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
Parameter ID bound to: 1095914585 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 8192 - type: integer
INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/rtl/clk_divider.sv:1]
Parameter COUNTER_BITS bound to: 32 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/rtl/clk_divider.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/rtl/interpreter.sv:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter ID bound to: 1095914585 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/rtl/interpreter.sv:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:66]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:125]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:199]
INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.sv:199]
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/rtl/fifo.sv:1]
Parameter DEPTH bound to: 8 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/rtl/fifo.sv:1]
INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/rtl/memory.sv:1]
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 8192 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Memory__parameterized0' [/eda/processor-ci-controller/rtl/memory.sv:1]
Parameter MEMORY_SIZE bound to: 4096 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Memory__parameterized0' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/rtl/controller.sv:1]
INFO: [Synth 8-638] synthesizing module 'klessydra_t0_2th_core' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/STR-Klessydra_top.vhd:64]
Parameter N_EXT_PERF_COUNTERS bound to: 0 - type: integer
Parameter INSTR_RDATA_WIDTH bound to: 32 - type: integer
Parameter N_HWLP bound to: 2 - type: integer
Parameter N_HWLP_BITS bound to: 4 - type: integer
INFO: [Synth 8-3491] module 'Program_Counter' declared at '/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:13' bound to instance 'Prg_Ctr' of component 'Program_Counter' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/STR-Klessydra_top.vhd:344]
INFO: [Synth 8-638] synthesizing module 'Program_Counter' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:55]
INFO: [Synth 8-256] done synthesizing module 'Program_Counter' (0#1) [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:55]
INFO: [Synth 8-3491] module 'CSR_Unit' declared at '/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-CSR_Unit.vhd:10' bound to instance 'CSR' of component 'CSR_Unit' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/STR-Klessydra_top.vhd:387]
INFO: [Synth 8-638] synthesizing module 'CSR_Unit' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-CSR_Unit.vhd:56]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-CSR_Unit.vhd:916]
INFO: [Synth 8-256] done synthesizing module 'CSR_Unit' (0#1) [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-CSR_Unit.vhd:56]
INFO: [Synth 8-3491] module 'Debug_UNIT' declared at '/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Debug_Unit.vhd:10' bound to instance 'DBG' of component 'Debug_Unit' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/STR-Klessydra_top.vhd:431]
INFO: [Synth 8-638] synthesizing module 'Debug_UNIT' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Debug_Unit.vhd:52]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Debug_Unit.vhd:99]
INFO: [Synth 8-256] done synthesizing module 'Debug_UNIT' (0#1) [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Debug_Unit.vhd:52]
INFO: [Synth 8-3491] module 'Pipeline' declared at '/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:10' bound to instance 'Pipe' of component 'Pipeline' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/STR-Klessydra_top.vhd:472]
INFO: [Synth 8-638] synthesizing module 'Pipeline' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:76]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:185]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:332]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:376]
WARNING: [Synth 8-614] signal 'instr_word_ID_lat' is read in the process but is not in the sensitivity list [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:261]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:961]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:982]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:1380]
INFO: [Synth 8-256] done synthesizing module 'Pipeline' (0#1) [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:76]
INFO: [Synth 8-256] done synthesizing module 'klessydra_t0_2th_core' (0#1) [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/STR-Klessydra_top.vhd:64]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/rtl/reset.sv:1]
Parameter CYCLES bound to: 32'sb00000000000000000000000000010100
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/rtl/reset.sv:32]
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/rtl/reset.sv:1]
WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/T02x.sv:230]
WARNING: [Synth 8-7071] port 'rst_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/T02x.sv:230]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/T02x.sv:230]
INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/T02x.sv:5]
WARNING: [Synth 8-3848] Net intr_o in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:25]
WARNING: [Synth 8-6014] Unused sequential element pc_update_logic[1].served_except_condition_lat_reg was removed. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:202]
WARNING: [Synth 8-6014] Unused sequential element pc_update_logic[0].served_except_condition_lat_reg was removed. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:202]
WARNING: [Synth 8-3848] Net branch_condition_pending in module/entity Program_Counter does not have driver. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:41]
WARNING: [Synth 8-3848] Net except_condition_pending_internal in module/entity Program_Counter does not have driver. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:77]
WARNING: [Synth 8-3848] Net mret_condition_pending_internal in module/entity Program_Counter does not have driver. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:71]
WARNING: [Synth 8-3848] Net debug_halted_o in module/entity Debug_UNIT does not have driver. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Debug_Unit.vhd:46]
WARNING: [Synth 8-6014] Unused sequential element RS1_Addr_IE_reg was removed. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:289]
WARNING: [Synth 8-6014] Unused sequential element RS2_Addr_IE_reg was removed. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:290]
WARNING: [Synth 8-6014] Unused sequential element RD_Addr_IE_reg was removed. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:291]
WARNING: [Synth 8-6014] Unused sequential element instruction_counter_reg was removed. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:586]
WARNING: [Synth 8-6014] Unused sequential element data_addr_internal_lat_reg was removed. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:1595]
WARNING: [Synth 8-6014] Unused sequential element state_IF_reg was removed. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:221]
WARNING: [Synth 8-3848] Net sec_lvl_o in module/entity klessydra_t0_2th_core does not have driver. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/STR-Klessydra_top.vhd:46]
WARNING: [Synth 8-3848] Net data_we_o_lat in module/entity klessydra_t0_2th_core does not have driver. [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/STR-Klessydra_top.vhd:118]
WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/T02x.sv:25]
WARNING: [Synth 8-7129] Port MSTATUS[1][31] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][30] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][29] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][28] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][27] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][26] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][25] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][24] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][23] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][22] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][21] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][20] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][19] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][18] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][17] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][16] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][15] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][14] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][13] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][12] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][11] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][10] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][9] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][8] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][7] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][6] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][5] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][4] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][31] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][30] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][29] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][28] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][27] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][26] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][25] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][24] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][23] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][22] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][21] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][20] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][19] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][18] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][17] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][16] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][15] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][14] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][13] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][12] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][11] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][10] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][9] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][8] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][7] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][6] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][5] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][4] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port debug_halted_o in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][31] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][30] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][29] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][28] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][27] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][26] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][25] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][24] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][23] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][22] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][21] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][20] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][19] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][18] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][17] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][16] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][15] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][14] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][13] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][12] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][11] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][10] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][9] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][8] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][7] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][6] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][5] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][4] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][3] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][2] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][1] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[1][0] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[0][31] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[0][30] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[0][29] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[0][28] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[0][27] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[0][26] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[0][25] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[0][24] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[0][23] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[0][22] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[0][21] in module Debug_UNIT is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 2416.941 ; gain = 787.879 ; free physical = 5010 ; free virtual = 27343
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2416.941 ; gain = 787.879 ; free physical = 5009 ; free virtual = 27342
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2416.941 ; gain = 787.879 ; free physical = 5009 ; free virtual = 27342
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2416.941 ; gain = 0.000 ; free physical = 5007 ; free virtual = 27340
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2562.418 ; gain = 0.000 ; free physical = 4993 ; free virtual = 27326
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2562.453 ; gain = 0.000 ; free physical = 4985 ; free virtual = 27318
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:29 ; elapsed = 00:00:27 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 4969 ; free virtual = 27303
---------------------------------------------------------------------------------
WARNING: [Synth 8-327] inferring latch for variable 'CSR_updating_logic[0].trap_hndlr_reg' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-CSR_Unit.vhd:126]
WARNING: [Synth 8-327] inferring latch for variable 'CSR_updating_logic[1].trap_hndlr_reg' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-CSR_Unit.vhd:126]
WARNING: [Synth 8-327] inferring latch for variable 'CSR_updating_logic[1].pc_IE_replicated_reg[0]' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-CSR_Unit.vhd:124]
WARNING: [Synth 8-327] inferring latch for variable 'CSR_updating_logic[1].pc_IE_replicated_reg[1]' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-CSR_Unit.vhd:124]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
running | 000 | 000
single_step_req | 001 | 011
halt_req | 010 | 001
halt | 011 | 010
single_step | 100 | 100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_DBU_reg' using encoding 'sequential' in module 'Debug_UNIT'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
reset | 000 | 001
normal | 001 | 010
data_grant_waiting | 010 | 100
data_valid_waiting | 011 | 011
debug | 100 | 110
sleep | 101 | 000
csr_instr_wait_state | 110 | 101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_IE_reg' using encoding 'sequential' in module 'Pipeline'
WARNING: [Synth 8-327] inferring latch for variable 'harc_ID_lat_reg' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:253]
WARNING: [Synth 8-327] inferring latch for variable 'instr_word_ID_lat_reg' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:251]
WARNING: [Synth 8-327] inferring latch for variable 'pc_ID_lat_reg' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:252]
WARNING: [Synth 8-327] inferring latch for variable 'fsm_IE_comb.PC_offset_wires_reg[1]' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:1177]
WARNING: [Synth 8-327] inferring latch for variable 'fsm_IE_comb.PC_offset_wires_reg[0]' [/var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd:1177]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
INIT | 001 | 00
RESET_COUNTER | 010 | 01
IDLE | 100 | 10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 3249 ; free virtual = 25588
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 2
2 Input 32 Bit Adders := 40
3 Input 32 Bit Adders := 1
2 Input 31 Bit Adders := 2
2 Input 24 Bit Adders := 2
2 Input 10 Bit Adders := 2
2 Input 8 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 4
2 Input 3 Bit Adders := 6
2 Input 1 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 2
+---Registers :
64 Bit Registers := 2
32 Bit Registers := 126
31 Bit Registers := 2
24 Bit Registers := 4
12 Bit Registers := 1
10 Bit Registers := 2
8 Bit Registers := 11
6 Bit Registers := 1
5 Bit Registers := 1
4 Bit Registers := 2
3 Bit Registers := 3
1 Bit Registers := 78
+---RAMs :
64K Bit (2048 X 32 bit) RAMs := 1
32K Bit (1024 X 32 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
4 Input 64 Bit Muxes := 1
2 Input 64 Bit Muxes := 1
48 Input 64 Bit Muxes := 2
2 Input 53 Bit Muxes := 9
13 Input 53 Bit Muxes := 1
10 Input 52 Bit Muxes := 2
2 Input 52 Bit Muxes := 5
3 Input 52 Bit Muxes := 1
7 Input 52 Bit Muxes := 1
6 Input 52 Bit Muxes := 2
4 Input 52 Bit Muxes := 1
8 Input 32 Bit Muxes := 6
4 Input 32 Bit Muxes := 35
2 Input 32 Bit Muxes := 208
29 Input 32 Bit Muxes := 6
5 Input 32 Bit Muxes := 6
21 Input 32 Bit Muxes := 1
3 Input 32 Bit Muxes := 1
7 Input 32 Bit Muxes := 6
2 Input 31 Bit Muxes := 4
48 Input 24 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
4 Input 8 Bit Muxes := 2
2 Input 8 Bit Muxes := 5
29 Input 8 Bit Muxes := 1
48 Input 8 Bit Muxes := 2
24 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 2
3 Input 6 Bit Muxes := 1
29 Input 5 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 6
20 Input 4 Bit Muxes := 1
7 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 12
68 Input 3 Bit Muxes := 1
21 Input 3 Bit Muxes := 1
5 Input 3 Bit Muxes := 4
3 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 16
7 Input 2 Bit Muxes := 1
48 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 4
2 Input 1 Bit Muxes := 316
4 Input 1 Bit Muxes := 114
29 Input 1 Bit Muxes := 8
5 Input 1 Bit Muxes := 16
13 Input 1 Bit Muxes := 3
6 Input 1 Bit Muxes := 3
3 Input 1 Bit Muxes := 8
8 Input 1 Bit Muxes := 2
22 Input 1 Bit Muxes := 64
7 Input 1 Bit Muxes := 91
48 Input 1 Bit Muxes := 22
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-3332] Sequential element (fsm_IE_comb.PC_offset_wires_reg[1][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (fsm_IE_comb.PC_offset_wires_reg[0][0]) is unused and will be removed from module Pipeline.
WARNING: [Synth 8-3332] Sequential element (debug_rdata_o_regi_53) is unused and will be removed from module Debug_UNIT.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:39 ; elapsed = 00:01:56 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 532 ; free virtual = 22895
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1 | LUT |
|Interpreter | memory_mux_selector | 256x1 | LUT |
+------------+---------------------+---------------+----------------+
Distributed RAM: Preliminary Mapping Report (see note below)
+----------------+------------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------+------------------------------------------+-----------+----------------------+------------------+
|processorci_top | u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 |
|processorci_top | u_Controller/Core_Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+----------------+------------------------------------------+-----------+----------------------+------------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:44 ; elapsed = 00:02:01 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 533 ; free virtual = 22896
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:48 ; elapsed = 00:02:05 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 534 ; free virtual = 22897
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+----------------+------------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------+------------------------------------------+-----------+----------------------+------------------+
|processorci_top | u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 |
|processorci_top | u_Controller/Core_Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+----------------+------------------------------------------+-----------+----------------------+------------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:52 ; elapsed = 00:02:09 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 522 ; free virtual = 22885
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:01:56 ; elapsed = 00:02:14 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 535 ; free virtual = 22897
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:01:56 ; elapsed = 00:02:14 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 535 ; free virtual = 22897
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:57 ; elapsed = 00:02:14 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 519 ; free virtual = 22882
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:01:57 ; elapsed = 00:02:14 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 532 ; free virtual = 22895
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:57 ; elapsed = 00:02:15 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 530 ; free virtual = 22893
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:58 ; elapsed = 00:02:15 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 535 ; free virtual = 22897
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 8|
|2 |CARRY4 | 432|
|3 |LUT1 | 284|
|4 |LUT2 | 541|
|5 |LUT3 | 1096|
|6 |LUT4 | 864|
|7 |LUT5 | 764|
|8 |LUT6 | 4464|
|9 |MUXF7 | 748|
|10 |MUXF8 | 338|
|11 |RAM256X1S | 384|
|12 |RAM32M | 2|
|13 |RAM32X1D | 4|
|14 |FDCE | 3336|
|15 |FDPE | 7|
|16 |FDRE | 1012|
|17 |FDSE | 4|
|18 |LD | 398|
|19 |LDP | 2|
|20 |IBUF | 2|
|21 |OBUF | 2|
|22 |OBUFT | 1|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:58 ; elapsed = 00:02:15 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 532 ; free virtual = 22895
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 20 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:51 ; elapsed = 00:02:13 . Memory (MB): peak = 2562.453 ; gain = 787.879 ; free physical = 5219 ; free virtual = 27581
Synthesis Optimization Complete : Time (s): cpu = 00:02:01 ; elapsed = 00:02:19 . Memory (MB): peak = 2562.453 ; gain = 933.391 ; free physical = 5219 ; free virtual = 27581
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2562.453 ; gain = 0.000 ; free physical = 5209 ; free virtual = 27572
INFO: [Netlist 29-17] Analyzing 2308 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Opt 31-138] Pushed 1 inverter(s) to 95 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2634.453 ; gain = 0.000 ; free physical = 5208 ; free virtual = 27571
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 790 instances were transformed.
LD => LDCE: 303 instances
LD => LDCE (inverted pins: G): 95 instances
LDP => LDPE: 2 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 384 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 6305c013
INFO: [Common 17-83] Releasing license: Synthesis
81 Infos, 145 Warnings, 2 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:02:08 ; elapsed = 00:02:27 . Memory (MB): peak = 2634.488 ; gain = 1317.465 ; free physical = 5211 ; free virtual = 27573
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 6748.408; main = 2037.125; forked = 5063.879
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 11689.098; main = 2634.457; forked = 9158.691
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2698.484 ; gain = 63.996 ; free physical = 5216 ; free virtual = 27578
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1a0228ab9
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2698.484 ; gain = 0.000 ; free physical = 5201 ; free virtual = 27563
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 1a0228ab9
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2825.484 ; gain = 0.000 ; free physical = 5044 ; free virtual = 27407
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1a0228ab9
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2825.484 ; gain = 0.000 ; free physical = 5043 ; free virtual = 27406
Phase 1 Initialization | Checksum: 1a0228ab9
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2825.484 ; gain = 0.000 ; free physical = 5043 ; free virtual = 27406
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 1a0228ab9
Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2825.484 ; gain = 0.000 ; free physical = 5047 ; free virtual = 27410
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 1a0228ab9
Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2825.484 ; gain = 0.000 ; free physical = 5047 ; free virtual = 27410
Phase 2 Timer Update And Timing Data Collection | Checksum: 1a0228ab9
Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2825.484 ; gain = 0.000 ; free physical = 5047 ; free virtual = 27410
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 38 inverters resulting in an inversion of 153 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 1258492e8
Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.49 . Memory (MB): peak = 2825.484 ; gain = 0.000 ; free physical = 5045 ; free virtual = 27408
Retarget | Checksum: 1258492e8
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 38 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 17a5af340
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.64 . Memory (MB): peak = 2825.484 ; gain = 0.000 ; free physical = 5044 ; free virtual = 27407
Constant propagation | Checksum: 17a5af340
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 1ee4419eb
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.8 . Memory (MB): peak = 2825.484 ; gain = 0.000 ; free physical = 5045 ; free virtual = 27408
Sweep | Checksum: 1ee4419eb
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
Phase 6 BUFG optimization
INFO: [Opt 31-194] Inserted BUFG u_klessydra_t0_2th_core/Pipe/fsm_IE_comb.PC_offset_wires_reg[0][31]_i_1_n_0_BUFG_inst to drive 31 load(s) on clock net u_klessydra_t0_2th_core/Pipe/fsm_IE_comb.PC_offset_wires_reg[0][31]_i_1_n_0_BUFG
INFO: [Opt 31-194] Inserted BUFG u_klessydra_t0_2th_core/Pipe/fsm_IE_comb.PC_offset_wires_reg[1][31]_i_2_n_0_BUFG_inst to drive 31 load(s) on clock net u_klessydra_t0_2th_core/Pipe/fsm_IE_comb.PC_offset_wires_reg[1][31]_i_2_n_0_BUFG
INFO: [Opt 31-193] Inserted 2 BUFG(s) on clock nets
Phase 6 BUFG optimization | Checksum: 15ae8e14e
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.92 . Memory (MB): peak = 2857.500 ; gain = 32.016 ; free physical = 5045 ; free virtual = 27408
BUFG optimization | Checksum: 15ae8e14e
INFO: [Opt 31-662] Phase BUFG optimization created 2 cells of which 2 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 15ae8e14e
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.94 . Memory (MB): peak = 2857.500 ; gain = 32.016 ; free physical = 5045 ; free virtual = 27408
Shift Register Optimization | Checksum: 15ae8e14e
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 15ae8e14e
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.98 . Memory (MB): peak = 2857.500 ; gain = 32.016 ; free physical = 5045 ; free virtual = 27408
Post Processing Netlist | Checksum: 15ae8e14e
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 16a40a859
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2857.500 ; gain = 32.016 ; free physical = 5045 ; free virtual = 27408
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2857.500 ; gain = 0.000 ; free physical = 5045 ; free virtual = 27408
Phase 9.2 Verifying Netlist Connectivity | Checksum: 16a40a859
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2857.500 ; gain = 32.016 ; free physical = 5045 ; free virtual = 27408
Phase 9 Finalization | Checksum: 16a40a859
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2857.500 ; gain = 32.016 ; free physical = 5045 ; free virtual = 27408
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 38 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 1 | 0 |
| BUFG optimization | 2 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 16a40a859
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2857.500 ; gain = 32.016 ; free physical = 5045 ; free virtual = 27408
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2857.500 ; gain = 0.000 ; free physical = 5045 ; free virtual = 27408
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 16a40a859
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2857.500 ; gain = 0.000 ; free physical = 5045 ; free virtual = 27408
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 16a40a859
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2857.500 ; gain = 0.000 ; free physical = 5045 ; free virtual = 27408
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2857.500 ; gain = 0.000 ; free physical = 5045 ; free virtual = 27408
Ending Netlist Obfuscation Task | Checksum: 16a40a859
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2857.500 ; gain = 0.000 ; free physical = 5045 ; free virtual = 27408
INFO: [Common 17-83] Releasing license: Implementation
22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2857.500 ; gain = 223.012 ; free physical = 5045 ; free virtual = 27408
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2889.516 ; gain = 0.000 ; free physical = 5046 ; free virtual = 27409
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 10b1ab5b3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2889.516 ; gain = 0.000 ; free physical = 5046 ; free virtual = 27409
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2889.516 ; gain = 0.000 ; free physical = 5046 ; free virtual = 27409
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 9ab11f0d
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2889.516 ; gain = 0.000 ; free physical = 5039 ; free virtual = 27402
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 17e35ca71
Time (s): cpu = 00:00:13 ; elapsed = 00:00:06 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5037 ; free virtual = 27400
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 17e35ca71
Time (s): cpu = 00:00:13 ; elapsed = 00:00:06 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5037 ; free virtual = 27400
Phase 1 Placer Initialization | Checksum: 17e35ca71
Time (s): cpu = 00:00:13 ; elapsed = 00:00:06 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5037 ; free virtual = 27400
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 191e2d7e4
Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5032 ; free virtual = 27395
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: e5855b12
Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5032 ; free virtual = 27395
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: e5855b12
Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5032 ; free virtual = 27395
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 14763f512
Time (s): cpu = 00:00:26 ; elapsed = 00:00:09 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5035 ; free virtual = 27398
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 295 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 139 nets or LUTs. Breaked 0 LUT, combined 139 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2896.543 ; gain = 0.000 ; free physical = 5043 ; free virtual = 27406
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 139 | 139 | 0 | 1 | 00:00:01 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 139 | 139 | 0 | 4 | 00:00:01 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 13442ca5f
Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5045 ; free virtual = 27408
Phase 2.4 Global Placement Core | Checksum: 181dccedf
Time (s): cpu = 00:00:28 ; elapsed = 00:00:11 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5045 ; free virtual = 27408
Phase 2 Global Placement | Checksum: 181dccedf
Time (s): cpu = 00:00:28 ; elapsed = 00:00:11 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5045 ; free virtual = 27408
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 2202e661f
Time (s): cpu = 00:00:28 ; elapsed = 00:00:11 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5045 ; free virtual = 27408
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2416775c5
Time (s): cpu = 00:00:29 ; elapsed = 00:00:12 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5044 ; free virtual = 27407
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 22890d83b
Time (s): cpu = 00:00:29 ; elapsed = 00:00:12 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5044 ; free virtual = 27407
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 21e0dd96b
Time (s): cpu = 00:00:29 ; elapsed = 00:00:12 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5044 ; free virtual = 27407
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1d9554322
Time (s): cpu = 00:00:33 ; elapsed = 00:00:16 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5040 ; free virtual = 27403
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 14b009769
Time (s): cpu = 00:00:34 ; elapsed = 00:00:16 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5039 ; free virtual = 27403
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 156739899
Time (s): cpu = 00:00:34 ; elapsed = 00:00:16 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5039 ; free virtual = 27403
Phase 3 Detail Placement | Checksum: 156739899
Time (s): cpu = 00:00:34 ; elapsed = 00:00:16 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5039 ; free virtual = 27403
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: c4341b03
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=9.074 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: fd3793dd
Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2896.543 ; gain = 0.000 ; free physical = 5040 ; free virtual = 27403
INFO: [Place 46-33] Processed net u_Controller/Interpreter/rst_core, BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: fd3793dd
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2896.543 ; gain = 0.000 ; free physical = 5040 ; free virtual = 27403
Phase 4.1.1.1 BUFG Insertion | Checksum: c4341b03
Time (s): cpu = 00:00:46 ; elapsed = 00:00:20 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5040 ; free virtual = 27403
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=9.074. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 10e0e7480
Time (s): cpu = 00:00:46 ; elapsed = 00:00:20 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5040 ; free virtual = 27403
Time (s): cpu = 00:00:46 ; elapsed = 00:00:20 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5040 ; free virtual = 27403
Phase 4.1 Post Commit Optimization | Checksum: 10e0e7480
Time (s): cpu = 00:00:46 ; elapsed = 00:00:20 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5040 ; free virtual = 27403
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 10e0e7480
Time (s): cpu = 00:00:46 ; elapsed = 00:00:20 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5040 ; free virtual = 27403
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 1x1|
|___________|___________________|___________________|
| South| 1x1| 2x2|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 10e0e7480
Time (s): cpu = 00:00:46 ; elapsed = 00:00:20 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5040 ; free virtual = 27403
Phase 4.3 Placer Reporting | Checksum: 10e0e7480
Time (s): cpu = 00:00:46 ; elapsed = 00:00:20 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5040 ; free virtual = 27403
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2896.543 ; gain = 0.000 ; free physical = 5040 ; free virtual = 27403
Time (s): cpu = 00:00:46 ; elapsed = 00:00:20 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5040 ; free virtual = 27403
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 143a5b14e
Time (s): cpu = 00:00:46 ; elapsed = 00:00:20 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5040 ; free virtual = 27403
Ending Placer Task | Checksum: d3a8de05
Time (s): cpu = 00:00:46 ; elapsed = 00:00:20 . Memory (MB): peak = 2896.543 ; gain = 7.027 ; free physical = 5040 ; free virtual = 27403
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:21 . Memory (MB): peak = 2896.543 ; gain = 39.043 ; free physical = 5040 ; free virtual = 27403
# report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
# report_utilization -file digilent_arty_a7_utilization_place.rpt
# report_io -file digilent_arty_a7_io.rpt
report_io: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2896.543 ; gain = 0.000 ; free physical = 5033 ; free virtual = 27397
# report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2896.543 ; gain = 0.000 ; free physical = 5033 ; free virtual = 27396
# report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 5ef4b6c1 ConstDB: 0 ShapeSum: 74b42744 RouteDB: 0
Post Restoration Checksum: NetGraph: cd5f6f66 | NumContArr: 88cd0cac | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2db7e714c
Time (s): cpu = 00:00:41 ; elapsed = 00:00:27 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5039 ; free virtual = 27403
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2db7e714c
Time (s): cpu = 00:00:41 ; elapsed = 00:00:27 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5039 ; free virtual = 27403
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2db7e714c
Time (s): cpu = 00:00:41 ; elapsed = 00:00:27 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5039 ; free virtual = 27403
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 3180cf420
Time (s): cpu = 00:00:56 ; elapsed = 00:00:32 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5028 ; free virtual = 27392
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.996 | TNS=0.000 | WHS=-0.066 | THS=-0.066 |
Router Utilization Summary
Global Vertical Routing Utilization = 0.0789485 %
Global Horizontal Routing Utilization = 0.109903 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 10988
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 10637
Number of Partially Routed Nets = 351
Number of Node Overlaps = 535
Phase 2 Router Initialization | Checksum: 28ad07466
Time (s): cpu = 00:01:01 ; elapsed = 00:00:33 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5020 ; free virtual = 27384
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 28ad07466
Time (s): cpu = 00:01:01 ; elapsed = 00:00:33 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5020 ; free virtual = 27384
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 2a7f9531f
Time (s): cpu = 00:01:06 ; elapsed = 00:00:34 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5028 ; free virtual = 27392
Phase 3 Initial Routing | Checksum: 2a7f9531f
Time (s): cpu = 00:01:06 ; elapsed = 00:00:34 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5028 ; free virtual = 27392
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 1481
Number of Nodes with overlaps = 7
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.777 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 207336c3f
Time (s): cpu = 00:01:17 ; elapsed = 00:00:38 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5006 ; free virtual = 27370
Phase 4 Rip-up And Reroute | Checksum: 207336c3f
Time (s): cpu = 00:01:17 ; elapsed = 00:00:38 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5006 ; free virtual = 27370
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 207336c3f
Time (s): cpu = 00:01:17 ; elapsed = 00:00:38 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5006 ; free virtual = 27370
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 207336c3f
Time (s): cpu = 00:01:17 ; elapsed = 00:00:38 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5006 ; free virtual = 27370
Phase 5 Delay and Skew Optimization | Checksum: 207336c3f
Time (s): cpu = 00:01:17 ; elapsed = 00:00:38 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5006 ; free virtual = 27370
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 206bff0be
Time (s): cpu = 00:01:18 ; elapsed = 00:00:39 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5006 ; free virtual = 27370
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.873 | TNS=0.000 | WHS=0.258 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 206bff0be
Time (s): cpu = 00:01:18 ; elapsed = 00:00:39 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5006 ; free virtual = 27370
Phase 6 Post Hold Fix | Checksum: 206bff0be
Time (s): cpu = 00:01:18 ; elapsed = 00:00:39 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5006 ; free virtual = 27370
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 2.85786 %
Global Horizontal Routing Utilization = 3.54241 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 206bff0be
Time (s): cpu = 00:01:18 ; elapsed = 00:00:39 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5004 ; free virtual = 27368
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 206bff0be
Time (s): cpu = 00:01:18 ; elapsed = 00:00:39 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5007 ; free virtual = 27371
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 25343574a
Time (s): cpu = 00:01:20 ; elapsed = 00:00:40 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5009 ; free virtual = 27373
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.873 | TNS=0.000 | WHS=0.258 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 25343574a
Time (s): cpu = 00:01:21 ; elapsed = 00:00:40 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5009 ; free virtual = 27373
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: deba1a1a
Time (s): cpu = 00:01:21 ; elapsed = 00:00:40 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5009 ; free virtual = 27373
Ending Routing Task | Checksum: deba1a1a
Time (s): cpu = 00:01:22 ; elapsed = 00:00:41 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5009 ; free virtual = 27373
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:24 ; elapsed = 00:00:42 . Memory (MB): peak = 2952.570 ; gain = 0.000 ; free physical = 5006 ; free virtual = 27370
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
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| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
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| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (140220)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (28306)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (140220)
-----------------------------
There are 5918 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
There are 82 register/latch pins with no clock driven by root clock pin: instr_grant_reg/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[0]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[10]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[11]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[12]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[13]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[14]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[15]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[16]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[17]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[18]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[19]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[1]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[20]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[21]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[22]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[23]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[24]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[25]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[26]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[27]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[28]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[29]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[2]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[30]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[31]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[3]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[4]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[5]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[6]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[7]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[8]/Q (HIGH)
There are 3696 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[9]/Q (HIGH)
There are 172 register/latch pins with no clock driven by root clock pin: u_Controller/Interpreter/core_reset_reg/Q (HIGH)
There are 32 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MCAUSE_internal_reg[0][31]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][0]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][10]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][11]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][12]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][13]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][14]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][15]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][16]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][17]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][18]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][19]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][1]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][20]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][21]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][22]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][23]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][24]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][25]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][26]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][27]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][28]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][29]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][2]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][30]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][31]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][3]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][4]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][5]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][6]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][7]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][8]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MEPC_internal_reg[0][9]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MIP_internal_reg[0][3]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MSTATUS_internal_reg[0][3]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].csr_access_denied_o_replicated_reg[0]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].csr_instr_done_replicated_reg[0]/Q (HIGH)
There are 32 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MCAUSE_internal_reg[1][31]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][0]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][10]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][11]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][12]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][13]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][14]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][15]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][16]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][17]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][18]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][19]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][1]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][20]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][21]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][22]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][23]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][24]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][25]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][26]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][27]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][28]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][29]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][2]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][30]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][31]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][3]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][4]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][5]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][6]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][7]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][8]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MEPC_internal_reg[1][9]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MIP_internal_reg[1][3]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].MSTATUS_internal_reg[1][3]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].csr_access_denied_o_replicated_reg[1]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].csr_instr_done_replicated_reg[1]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][0]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][10]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][11]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][12]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][13]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][14]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][15]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][16]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][17]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][18]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][19]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][1]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][20]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][21]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][22]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][23]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][24]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][25]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][26]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][27]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][28]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][29]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][2]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][30]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][31]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][3]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][4]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][5]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][6]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][7]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][8]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[0][9]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][0]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][10]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][11]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][12]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][13]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][14]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][15]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][16]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][17]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][18]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][19]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][1]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][20]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][21]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][22]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][23]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][24]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][25]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][26]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][27]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][28]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][29]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][2]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][30]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][31]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][3]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][4]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][5]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][6]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][7]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][8]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].pc_IE_replicated_reg[1][9]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/FSM_sequential_state_IE_reg[0]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/FSM_sequential_state_IE_reg[1]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/FSM_sequential_state_IE_reg[2]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/RS1_Data_IE_reg[0]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/RS1_Data_IE_reg[1]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/amo_load_reg/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/amo_load_skip_reg/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/amo_store_lat_reg/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[0]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[10]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[11]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[12]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[13]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[14]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[15]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[16]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[17]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[18]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[19]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[1]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[20]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[21]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[22]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[23]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[24]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[25]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[26]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[27]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[28]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[29]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[2]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[30]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[31]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[32]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[33]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[34]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[35]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[36]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[37]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[38]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[39]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[3]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[40]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[41]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[42]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[43]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[44]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[45]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[46]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[47]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[48]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[49]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[4]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[51]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[5]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[6]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[7]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[8]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE_reg[9]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][0]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][10]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][11]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][12]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][13]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][14]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][15]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][16]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][17]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][18]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][19]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][1]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][20]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][21]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][22]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][23]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][24]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][25]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][26]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][27]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][28]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][29]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][2]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][30]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][3]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][4]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][5]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][6]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][7]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][8]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[0][9]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][0]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][10]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][11]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][12]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][13]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][14]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][15]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][16]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][17]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][18]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][19]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][1]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][20]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][21]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][22]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][23]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][24]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][25]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][26]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][27]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][28]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][29]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][2]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][30]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][3]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][4]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][5]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][6]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][7]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][8]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/flush_cycle_count_reg[1][9]/Q (HIGH)
There are 316 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/harc_IE_wire_reg[0]/Q (HIGH)
There are 126 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/instr_rvalid_IE_reg/Q (HIGH)
There are 46 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/instr_rvalid_state_reg/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/instr_word_IE_wire_reg[20]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/instr_word_IE_wire_reg[21]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/instr_word_IE_wire_reg[7]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/instr_word_IE_wire_reg[8]/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/pass_BEQ_ID_reg/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/pass_BGEU_ID_reg/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/pass_BGE_ID_reg/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/pass_BLTU_ID_reg/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/pass_BLT_ID_reg/Q (HIGH)
There are 64 register/latch pins with no clock driven by root clock pin: u_klessydra_t0_2th_core/Pipe/pass_BNE_ID_reg/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (28306)
----------------------------------------------------
There are 28306 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (1)
-------------------------------
There is 1 port with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.898 0.000 0 1 0.274 0.000 0 1 4.500 0.000 0 2
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sck {0.000 50.000} 100.000 10.000
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.898 0.000 0 1 0.274 0.000 0 1 4.500 0.000 0 2
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_arty_a7_route_status.rpt
# report_drc -file digilent_arty_a7_drc.rpt
Command: report_drc -file digilent_arty_a7_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/T02x/T02x/digilent_arty_a7_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_arty_a7_power.rpt
Command: report_power -file digilent_arty_a7_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "digilent_arty_a7_100t.bit"
Command: write_bitstream -force digilent_arty_a7_100t.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].trap_hndlr_reg0 is a gated clock net sourced by a combinational pin u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].trap_hndlr_reg[0]_i_1/O, cell u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].trap_hndlr_reg[0]_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].trap_hndlr_reg0 is a gated clock net sourced by a combinational pin u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].trap_hndlr_reg[1]_i_1/O, cell u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].trap_hndlr_reg[1]_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 3 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_arty_a7_100t.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 3267.871 ; gain = 236.465 ; free physical = 4639 ; free virtual = 27009
# exit
INFO: [Common 17-206] Exiting Vivado at Sat Apr 26 22:36:35 2025...
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
[Pipeline] dir
Running in /var/jenkins_home/workspace/T02x/T02x
[Pipeline] {
[Pipeline] echo
Flashing FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p T02x -b digilent_arty_a7_100t -l
Makefile executed successfully.
Makefile output:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit
empty
Jtag frequency : requested 10.00MHz -> real 10.00MHz
Open file DONE
Parse file DONE
load program
Load SRAM: [================ ] 31.00%
Load SRAM: [================================ ] 63.00%
Load SRAM: [================================================ ] 95.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
[Pipeline] echo
Testing FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyUSB1
Test for FPGA in /dev/ttyUSB1
[Pipeline] sh
+ python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459 -ctm
32
Connected to FPGA with ID: b'ARTY'
Checking for sync keyword...
Sync keyword matched.
Testsuite configurated.
Running tests: RV32I in /eda/processor_ci_tests/tests/RV32I
Running basic tests in /eda/processor_ci_tests/tests/RV32I/basic, with breakpoint 60
Running test: 000-addi.hex
Running test: 001-sw.hex
Running test: 002-slti.hex
Running test: 003-sltiu.hex
Running test: 004-xori.hex
Running test: 005-ori.hex
Running test: 006-andi.hex
Running test: 007-slli.hex
Running test: 008-srli.hex
Running test: 009-srai.hex
Running test: 010-lui.hex
Running test: 011-auipc.hex
Running test: 012-jal.hex
Running test: 013-jalr.hex
Running test: 014-beq.hex
Running test: 015-bne.hex
Running test: 016-blt.hex
Running test: 017-bge.hex
Running test: 018-bltu.hex
Running test: 019-bgeu.hex
Running test: 020-lb.hex
Running test: 021-lh.hex
Running test: 022-lw.hex
Running test: 023-lbu.hex
Running test: 024-lhu.hex
Running test: 025-sb.hex
Running test: 026-sh.hex
Running test: 027-add.hex
Running test: 028-sub.hex
Running test: 029-sll.hex
Running test: 030-slt.hex
Running test: 031-sltu.hex
Running test: 032-xor.hex
Running test: 033-srl.hex
Running test: 034-sra.hex
Running test: 035-or.hex
Running test: 036-and.hex
Running test: 037-fence.hex
Running test: 038-ecall.hex
Running test: 039-ebreak.hex
Running test: 040-timeout.hex
Running test: 041-forwarding.hex
Running test: 042-forwarding-lw.hex
JUnit XML report generated: test_results_1745721422.198997.xml
All tests finished.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: UNSTABLE
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