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Start of Pipeline - (29 sec in block)
node - (28 sec in block)
node block - (27 sec in block)
stage - (2 sec in block)Git Clone
stage block (Git Clone) - (1.5 sec in block)
sh - (0.45 sec in self)rm -rf T02x
sh - (0.9 sec in self)git clone --recursive --depth=1 https://github.com/klessydra/T02x T02x
stage - (9.8 sec in block)Simulation
stage block (Simulation) - (9.3 sec in block)
dir - (8.9 sec in block)T02x
dir block - (8.6 sec in block)
sh - (8.4 sec in self)/eda/oss-cad-suite/bin/ghdl -a --std=08 klessydra-t0-2th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-t0-2th/PKG_RiscV_Klessydra.vhd klessydra-t0-2th/RTL-CSR_Unit.vhd klessydra-t0-2th/RTL-Debug_Unit.vhd klessydra-t0-2th/RTL-Processing_Pipeline.vhd klessydra-t0-2th/RTL-Program_Counter_unit.vhd klessydra-t0-2th/STR-Klessydra_top.vhd
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.86 sec in block)T02x
dir block - (0.61 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (13 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (12 sec in block)
parallel - (12 sec in block)
parallel block (Branch: colorlight_i9) - (51 ms in block)
stage - (10 sec in block)colorlight_i9
stage block (colorlight_i9) - (9.6 sec in block)
lock - (8.9 sec in block)colorlight_i9
lock block - (7.5 sec in block)
stage - (3.4 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.2 sec in block)
dir - (1.6 sec in block)T02x
dir block - (1.1 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.65 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p T02x -b colorlight_i9
stage - (1.7 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.6 sec in block)
getContext - (0.16 sec in self)
stage - (1.3 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.69 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (11 sec in block)
stage - (10 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (9.9 sec in block)
lock - (9 sec in block)digilent_arty_a7_100t
lock block - (7.8 sec in block)
stage - (3.5 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.8 sec in block)
dir - (2.1 sec in block)T02x
dir block - (1.5 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (0.92 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p T02x -b digilent_arty_a7_100t
stage - (1.7 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.7 sec in block)
getContext - (0.16 sec in self)
stage - (1.5 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.73 sec in block)
getContext - (0.16 sec in self)
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.52 sec in block)
junit - (0.25 sec in self)**/test-reports/*.xml