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Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Klessydra-T02
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf T02x/ build/
[Pipeline] sh
+ git clone https://github.com/klessydra/T02x.git
Cloning into 'T02x'...
[Pipeline] sh
+ cd T02x
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (GHDL)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ghdl -a --std=08 T02x/klessydra-t0-2th/PKG_RiscV_Klessydra_thread_parameters.vhd T02x/klessydra-t0-2th/PKG_RiscV_Klessydra.vhd T02x/klessydra-t0-2th/RTL-CSR_Unit.vhd T02x/klessydra-t0-2th/RTL-Debug_Unit.vhd T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd T02x/klessydra-t0-2th/STR-Klessydra_top.vhd
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:81:12:warning: declaration of "MTVEC" hides port "MTVEC" [-Whide]
    signal MTVEC                     : in    std_logic_vector(31 downto 0);
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:82:12:warning: declaration of "instr_gnt_i" hides port "instr_gnt_i" [-Whide]
    signal instr_gnt_i, taken_branch : in    std_logic;
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:82:25:warning: declaration of "taken_branch" hides port "taken_branch" [-Whide]
    signal instr_gnt_i, taken_branch : in    std_logic;
                        ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:83:12:warning: declaration of "wfi_condition_pending" hides signal "wfi_condition_pending" [-Whide]
    signal wfi_condition_pending     : inout std_logic;
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:84:12:warning: declaration of "set_wfi_condition" hides port "set_wfi_condition" [-Whide]
    signal set_wfi_condition         : in    std_logic;
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:85:12:warning: declaration of "taken_branch_pending" hides port "taken_branch_pending" [-Whide]
    signal taken_branch_pending      : inout std_logic;
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:86:12:warning: declaration of "irq_pending" hides port "irq_pending" [-Whide]
    signal irq_pending               : in    std_logic;
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:87:12:warning: declaration of "set_except_condition" hides port "set_except_condition" [-Whide]
    signal set_except_condition      : in    std_logic;
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:88:12:warning: declaration of "set_mret_condition" hides port "set_mret_condition" [-Whide]
    signal set_mret_condition        : in    std_logic;
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:89:12:warning: declaration of "pc" hides signal "pc" [-Whide]
    signal pc                        : inout std_logic_vector(31 downto 0);
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:90:12:warning: declaration of "taken_branch_pc_lat" hides port "taken_branch_pc_lat" [-Whide]
    signal taken_branch_pc_lat       : in    std_logic_vector(31 downto 0);
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:91:12:warning: declaration of "incremented_pc" hides port "incremented_pc" [-Whide]
    signal incremented_pc            : in    std_logic_vector(31 downto 0);
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:92:12:warning: declaration of "boot_pc" hides signal "boot_pc" [-Whide]
    signal boot_pc                   : in    std_logic_vector(31 downto 0);
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:93:12:warning: declaration of "pc_update_enable" hides signal "pc_update_enable" [-Whide]
    signal pc_update_enable          : in    std_logic;
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:94:12:warning: declaration of "served_except_condition" hides port "served_except_condition" [-Whide]
    signal served_except_condition   : out   std_logic;
           ^
T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd:95:12:warning: declaration of "served_mret_condition" hides port "served_mret_condition" [-Whide]
    signal served_mret_condition     : out   std_logic) is
           ^
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS