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Start of Pipeline - (59 sec in block)
node - (59 sec in block)
node block - (13 sec in block)
stage - (3.2 sec in block)Git Clone
stage block (Git Clone) - (2.7 sec in block)
sh - (0.59 sec in self)rm -rf *.xml
sh - (0.49 sec in self)rm -rf SprintRV
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/CastoHu/SprintRV SprintRV
stage - (1.9 sec in block)Simulation
stage block (Simulation) - (1.4 sec in block)
dir - (0.97 sec in block)SprintRV
dir block - (0.64 sec in block)
sh - (0.45 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s core_top -I rtl/core/include/ rtl/core/core_top.v rtl/core/ctrl/ctrl.v rtl/core/dec/id.v rtl/core/dec/id_ex.v rtl/core/exu/div.v rtl/core/exu/ex.v rtl/core/exu/ex_mem.v rtl/core/ifu/bp.v rtl/core/ifu/if_id.v rtl/core/ifu/ifu.v rtl/core/include/defines.v rtl/core/lsu/mem.v rtl/core/lsu/mem_wb.v rtl/core/wb/csr.v rtl/core/wb/gpr.v
stage - (0.91 sec in block)Utilities
stage block (Utilities) - (0.34 sec in block)
getContext - (0.15 sec in self)
stage - (5.5 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 sec in block)
getContext - (0.28 sec in self)
parallel - (4.3 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4 sec in block)
stage - (3.5 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3.2 sec in block)
getContext - (0.36 sec in self)
stage - (0.91 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.93 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.16 sec in self)
stage - (0.69 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.74 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.52 sec in block)
junit - (0.25 sec in self)**/*.xml