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Start of Pipeline - (13 min in block)
node - (13 min in block)
node block - (1 min 59 sec in block)
stage - (3.6 sec in block)Git Clone
stage block (Git Clone) - (3.1 sec in block)
sh - (0.58 sec in self)rm -rf SparrowRV
sh - (2.2 sec in self)git clone --recursive --depth=1 https://github.com/xiaowuzxc/SparrowRV SparrowRV
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.86 sec in block)SparrowRV
dir block - (0.58 sec in block)
sh - (0.39 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s core -I rtl/ rtl/config.v rtl/defines.v rtl/core/core.v rtl/core/csr.v rtl/core/div.v rtl/core/dpram.v rtl/core/idex.v rtl/core/iram.v rtl/core/regs.v rtl/core/rstc.v rtl/core/sctr.v rtl/core/trap.v
stage - (3.1 sec in block)Utilities
stage block (Utilities) - (2.1 sec in block)
dir - (1.5 sec in block)SparrowRV
dir block - (1 sec in block)
sh - (0.63 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (1 min 49 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (1 min 48 sec in block)
parallel - (1 min 47 sec in block)
parallel block (Branch: colorlight_i9) - (0.22 sec in block)
stage - (8 sec in block)colorlight_i9
stage block (colorlight_i9) - (7.6 sec in block)
lock - (5.9 sec in block)colorlight_i9
lock block - (4.8 sec in block)
stage - (2.2 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1.6 sec in block)
dir - (1 sec in block)SparrowRV
dir block - (0.75 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.46 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p SparrowRV -b colorlight_i9
stage - (0.93 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (0.7 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.39 sec in block)
getContext - (0.17 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (1 min 46 sec in block)
stage - (1 min 44 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (1 min 43 sec in block)
lock - (1 min 42 sec in block)digilent_arty_a7_100t
lock block - (1 min 14 sec in block)
stage - (1 min 11 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1 min 10 sec in block)
dir - (1 min 9 sec in block)SparrowRV
dir block - (1 min 8 sec in block)
echo - (0.33 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (1 min 8 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p SparrowRV -b digilent_arty_a7_100t
stage - (1.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.84 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.44 sec in block)
getContext - (0.16 sec in self)
stage - (1.4 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1 sec in block)
junit - (0.53 sec in self)**/test-reports/*.xml