Console Output

+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Risco-5 -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/Risco-5/Risco-5/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Common 17-69] Command failed: File '/eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv' does not exist
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 296, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.