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Start of Pipeline - (6 min 32 sec in block)
node - (6 min 31 sec in block)
node block - (6 min 31 sec in block)
stage - (2.9 sec in block)Git Clone
stage block (Git Clone) - (2.4 sec in block)
sh - (0.47 sec in self)rm -rf *.xml
sh - (0.48 sec in self)rm -rf Risco-5
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/JN513/Risco-5.git Risco-5
stage - (2.1 sec in block)Simulation
stage block (Simulation) - (1.6 sec in block)
dir - (1 sec in block)Risco-5
dir block - (0.64 sec in block)
sh - (0.42 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s soc_tb -I src/core/ src/core/alu.v src/core/alu_control.v src/core/control_unit.v src/core/core.v src/core/csr_unit.v src/core/immediate_generator.v src/core/mdu.v src/core/mux.v src/core/pc.v src/core/registers.v tests/soc_test.v src/peripheral/bus.v src/peripheral/fifo.v src/peripheral/gpios.v src/peripheral/gpio.v src/peripheral/leds.v src/peripheral/memory.v src/peripheral/pwm.v src/peripheral/soc.v src/peripheral/uart_rx.v src/peripheral/uart_tx.v src/peripheral/uart.v
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.88 sec in block)Risco-5
dir block - (0.62 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (6 min 23 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (6 min 22 sec in block)
parallel - (6 min 22 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (6 min 21 sec in block)
stage - (6 min 21 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (6 min 21 sec in block)
lock - (6 min 20 sec in block)digilent_arty_a7_100t
lock block - (6 min 20 sec in block)
stage - (6 min 8 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (6 min 7 sec in block)
dir - (6 min 7 sec in block)Risco-5
dir block - (6 min 7 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (6 min 6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Risco-5 -b digilent_arty_a7_100t
stage - (5.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.6 sec in block)
dir - (4.2 sec in block)Risco-5
dir block - (4 sec in block)
echo - (0.16 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Risco-5 -b digilent_arty_a7_100t -l
stage - (6.7 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (6.4 sec in block)
echo - (0.15 sec in self)Testing FPGA digilent_arty_a7_100t.
sh - (0.46 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (5.6 sec in self)python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459
stage - (0.87 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.66 sec in block)
junit - (0.42 sec in self)**/*.xml